MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 33

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 24:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
DQ[7:0]
W/R#
DQS
CE#
ALE
CLK
CLE
t CALS
t CALS
t CKL
t CS
Synchronous DDR Data Output Cycles
t CK
t CKH
Notes:
t CALS
2. See Figure 21 on page 28 for details of W/R# behavior.
3.
4. For W/R# transitioning HIGH: DQ[7:0] and DQS go to tri-state.
5. For W/R# transitioning LOW: DQ[7:0] drives current state and DQS goes LOW.
6. After final data output, DQ[7:0] is driven until W/R# goes HIGH, but is not valid.
1. When CE# remains LOW,
t CAD
quent command or data output cycle(s).
t
t DQSD
AC is the DQ output window relative to CLK and is the long-term component of DQ skew.
t WRCK
Micron Confidential and Proprietary
t CALS
t CALS
8Gb Asychronous/Synchronous NAND Flash Memory
t HP
t DQSCK
t AC
t HP
t DQSQ
t
CAD begins at the rising edge of the clock after
t DQSCK
t HP
33
t DVW
t QH
t DQSCK
D 0
t DVW
t DQSCK
t QH
D 1
t DQSQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Undefined (driven by NAND)
t DVW
D 2
t HP
t CALH
t CALH
t HP
t DQSCK
t CALS
t CALS
t HP
t DQSQ
t DQSCK
D N-2
t CKWR
t DVW
t QH
D N-1
©2008 Micron Technology, Inc. All rights reserved.
Don’t Care
t DVW
t QH
D N
t DQSQ
Bus Operation
t
t CALS
CKWR for subse-
Data Transitioning
t ALH
t CLH
t DQSHZ
t CH
t CAD starts
here
Advance
1