MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet
MPC2605ZP83
Specifications of MPC2605ZP83
Available stocks
Related parts for MPC2605ZP83
MPC2605ZP83 Summary of contents
Page 1
... Single Clock Operation • Compliant with IEEE Standard 1149.1 Test Access Port (JTAG) • Supports up to Four Processors in a Shared Cache Configuration • High Board Density 25 mm 241 PBGA Package For More Information On This Product, Go to: www.freescale.com ZP PACKAGE PBGA ZP PACKAGE CASE 1138-0 ...
Page 2
... LRU 2 Integrated Secondary Cache for Microprocessors For More Information On This Product, BLOCK DIAGRAM RD/WR A27, A28 DATA RAM RD/ TAG RAM That Implement PowerPC Architecture Go to: www.freescale.com COPY-BACK BUFFER DH0 – DH31 DL0 – DL31 DP0 – DP7 WAY SELECT COMPARE MOTOROLA ...
Page 3
... DH14 DH10 DL1 DL4 DH1 DP1 DH13 DH11 DL0 DL3 DL6 DH0 DH15 DH12 DH9 DH8 DL2 DL5 TOP VIEW That Implement PowerPC Architecture Go to: www.freescale.com MPC2605 DL22 DP6 DL25 DL27 DL29 DL30 DL23 DL24 DL26 DL28 DL31 DP7 AP3 AP2 ...
Page 4
... I MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor configuration as the third CPU BG. I MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor configuration as the fourth CPU BG. I CPU bus request input. That Implement PowerPC Architecture Go to: www.freescale.com Description 256KB 0 512KB; A26 = 0 1 512KB ...
Page 5
... I Data bus grant input. Comes from system arbiter, used to start data tenure for bus operations where MPC2605 is the bus master. I Causes cache to write back dirty lines and clears all tag valid bits. That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D Description 5 ...
Page 6
... Write through status input from processor bus. When tied to ground, the MPC2605 will operate in write-through mode only (no copy back). Supply Power supply: 3.3 V ± 5%. Supply Ground. SS — No connection. There is no connection to the chip. That Implement PowerPC Architecture Go to: www.freescale.com Description MOTOROLA ...
Page 7
... IH Cycle Time = 15 ns Cycle Time = 12 ns 3.0 V, Cycle Time = 15 ns That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits ...
Page 8
... Reference Min Max 1 12 — 2 4.8 — — ±200 3 3.5 — 3 2.5 — — — 6 — — — That Implement PowerPC Architecture Go to: www.freescale.com Symbol Typ Max Unit out I/O Symbol Max Unit R 26.5 C 23.2 C 15.9 C 6.6 C/W JC Termination to 1.5 V MPC2605-66 ...
Page 9
... ARTRY, L2 BR, write back data, invalidate tag (flush block address-only) Hit Clean No action (clean block address-only) Hit Dirty ARTRY, L2 BR, write back data, reset dirty bit (clean block address-only) Hit Invalidate tag (kill block address-only) That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D Notes ...
Page 10
... NOTE: In all snoop push cases sampled the cycle after the ARTRY window asserted in this cycle will be immediately negated and an assertion will be ignored TRANSFER ATTRIBUTES GENERATED FOR L2 COPY BACK TT0 – TT4 TBST 00010 0 10 Integrated Secondary Cache for Microprocessors For More Information On This Product, MPC2605 Response That Implement PowerPC Architecture Go to: www.freescale.com MOTOROLA ...
Page 11
... However, some chipsets are designed with the memory controller and DMA bridge partitioned into different devices. In That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D CFG1, and CFG2 should all be tied low. parts to have CFG0 tied low and CFG1 tied high ...
Page 12
... MPC2605 becomes the slave by driving L2 CLAIM. Transactions can be aborted by any device on the bus by asserting ARTRY. ARTRY may be asserted at any time after TS is asserted, but must be held through That Implement PowerPC Architecture Go to: www.freescale.com TS MOTOROLA ...
Page 13
... Data Bus Parking The MPC2605 has the ability to respond to a processor read or write hit starting in the cycle after the processor has asserted TS. This is referred That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D 13 ...
Page 14
... The timing of the assertion of AACK for a pipelined cache hit is dependent on the completion of the previous transaction. For explanation purposes, the previous transaction will be referred to as transaction one. The pipelined cache hit will be referred to as transaction two. That Implement PowerPC Architecture Go to: www.freescale.com MOTOROLA ...
Page 15
... Because each MPC2605 has its own castout buffer (COB possible for situations to arise where more than one device is needed copy-back operation. Under normal circumstances, each device will enter castout conditions at different times. In these cases, when a device determines that it needs castout, That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D 15 ...
Page 16
... This state is entered after PWRDN is synchronized and both the address and data buses are idle. All data is retained while in the sleep state. The behavior of the MPC2605 on negation of PWRDN is dependent on the state the rising That Implement PowerPC Architecture Go to: www.freescale.com MOTOROLA ...
Page 17
... L2 TAG CLR. L2 UPDATE INH When L2 UPDATE INH is asserted, the MPC2605 is disabled from responding to cacheable transactions. Bus transactions continue to be monitored so that as soon as L2 UPDATE INH is negated, the MPC204GA can participate in the next transaction. That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D 17 ...
Page 18
... TA in the next cycle. CPU DBG does not affect the timing of L2 CLAIM or AACK. The write hit timing is virtually the same. The only difference is the processor drives the data instead of the MPC2605 Figure 1. Burst Read (or Write) Hit That Implement PowerPC Architecture Go to: www.freescale.com MOTOROLA ...
Page 19
... For More Information On This Product, transfer. Therefore, it must hold off on its assertion of AACK for a pipelined TS until the data tenure for the first TS is done. The MPC2605 asserts AACK at the same time as the fourth TA for data tenures that it controls That Implement PowerPC Architecture Go to: www.freescale.com MPC2605 ...
Page 20
... TA of the read miss. This is because the MPC2605 is not in control of TA for the first access and must, therefore, wait until the first access' data tenure is complete before it can drive AACK true for the read hit That Implement PowerPC Architecture Go to: www.freescale.com MOTOROLA 12 ...
Page 21
... For More Information On This Product, fourth TA of each data tenure. This is a requirement for data streaming. Note also that DBB is not shown. For proper operation in Fast L2 mode, the DBB pin of the MPC2605 must be tied to a pull-up resistor That Implement PowerPC Architecture Go to: www.freescale.com MPC2605 ...
Page 22
... WT is asserted by the processor when it asserts TS. The speed that a write-through operation completes, is solely dependent on the memory controller. The timing shown here assumes that the memory controller has a write buffer that can accept data this quickly That Implement PowerPC Architecture Go to: www.freescale.com MOTOROLA ...
Page 23
... Note that the copy-back operation occurs after the processor request is satisfied. In addition, no delay is added to the processor transaction. It proceeds as fast as the memory controller will allow That Implement PowerPC Architecture Go to: www.freescale.com MPC2605 ...
Page 24
... BR signal is not asserted, the MPC2605 will start sampling L2 BG, the cycle after the BR window. Note that the MPC2605 cannot do a 2-1-1-1 copy back burst. The earliest that it can handle the first assertion two cycles after its assertion of TS That Implement PowerPC Architecture Go to: www.freescale.com MOTOROLA 12 ...
Page 25
... BR window, the MPC2605 will negate L2 BR. It will also ignore assertions of L2 BG. This allows the processor to write back its dirty cache line. At this time, the MPC2605 will either update or invalidate its copy depending on whether snoop read or snoop write That Implement PowerPC Architecture Go to: www.freescale.com MPC2605 ...
Page 26
... CPU DBG. Figure 9 shows the response for a read hit from the MPC2605, as gated by the assertion of CPU DBG. The fastest response possible in a system that does not park CPU DBG is 3-1-1- That Implement PowerPC Architecture Go to: www.freescale.com MOTOROLA ...
Page 27
... Min Max t 30 — — CKH t 12 — CKL CKZ CKX t 2 — — CKH CKL CKZ Figure 10. TAP Controller Timing That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D Termination to 1.5 V MPC2605-83 Unit Notes Min Max 30 — — — — — CKX 27 ...
Page 28
... CLAMP instruction is active. HIGHZ TAP INSTRUCTION The HIGHZ instruction is provided to allow all the outputs to be placed in an inactive drive state (High-Z). During the HIGHZ instruction, the bypass register is connected between TDI and TDO. That Implement PowerPC Architecture Go to: www.freescale.com MOTOROLA ...
Page 29
... V remain unconnected. SELECT DR-SCAN CAPTURE-DR 0 SHIFT- EXIT1-DR 0 PAUSE- EXIT2-DR 1 UPDATE- Figure 11. TAP Controller State Diagram That Implement PowerPC Architecture Go to: www.freescale.com MPC2605 through a 1K resistor. TDO should DD SELECT IR-SCAN CAPTURE-IR 0 SHIFT- EXIT1-IR 0 PAUSE- EXIT2-IR 1 UPDATE-IR 0 ...
Page 30
... DOE 36 DOE 37 DOE 38 DOE 39 DOE 40 DOE 41 DOE 42 DOE 43 DOE 44 DOE 45 DOE That Implement PowerPC Architecture Go to: www.freescale.com Bit/Pin Bit/Pin Output Name Type Enable DL26 I/O DOE DL27 I/O DOE DL28 I/O DOE DL29 I/O DOE DL30 I/O DOE DL31 I/O ...
Page 31
... DOE 114 DOE 115 DOE 116 DOE 117 That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D Bit/Pin Bit/Pin Output Name Type Enable DH12 I/O DOE DH13 I/O DOE DH14 I/O DOE DH15 I/O ...
Page 32
... AOE 167 AOE AOE 168 AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE AOE That Implement PowerPC Architecture Go to: www.freescale.com Bit/Pin Bit/Pin Output Name Type Enable AP1 I/O AOE AP2 I/O AOE AP3 I/O AOE APE Output APEOE ...
Page 33
... Full Part Numbers — MPC2605ZP66 MOTOROLA Integrated Secondary Cache for Microprocessors For More Information On This Product, ORDERING INFORMATION (Order by Full Part Number) MPC 2605 Blank = Trays Tape and Reel Speed ( MHz MHz) Package (ZP = PBGA) MPC2605ZP83 MPC2605ZP66R MPC2605ZP83R That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D 33 ...
Page 34
... C 0. 18X SIDE VIEW b 241 0. 0. That Implement PowerPC Architecture Go to: www.freescale.com C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM C. MILLIMETERS DIM MIN MAX A --- 2.05 A1 0.50 0.70 A2 0.95 1. ...
Page 35
... Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA Integrated Secondary Cache for Microprocessors For More Information On This Product, That Implement PowerPC Architecture Go to: www.freescale.com MPC2605/D 35 ...
Page 36
... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 MPC2605/D For More Information On This Product, Go to: www.freescale.com ...