MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 15

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

be the slave device for the transaction. Since, for burst
operations, the MPC2605 always asserts TA for four
consecutive clock cycles, the end of the data tenure for
transaction one will be at a deterministic clock cycle.
In this case, AACK for transaction two can be asserted
coinciding with the last assertion of TA for transaction
one. If transaction one is not a cache hit, the MPC2605
will wait until after the data tenure for transaction one
has completed before asserting AACK to complete the
address tenure of transaction two.
MEMORY COHERENCE
and modifies it, a situation has arisen that the main
memory now contains irrelevant or stale data. Given
that most systems support some form of DMA, there
must exist a means that forces the processor to write
this modified or dirty data back to main memory. The
DMA bridge is responsible for generating bus
transactions to ensure that main memory locations
accessed by DMA operations do not contain stale data.
These transactions, called snoops, come in three
different categories, each will be discussed below.
check to see if they have dirty copies of the memory
location specified in the snoop transaction. If either
device does have a dirty copy it will assert ARTRY
and make use of the opportunity presented in the BR
window to write this data back to main memory.
both the processor's L1 cache and in the MPC2605. In
cases such as these, snoop transactions should cause
the processor to write its data back to memory, since it
is by definition more recent than the data in the
MPC2605. Since ARTRY is a shared signal and it
cannot be determined which devices are driving it, the
MPC2605 samples CPU BR in the BR window to
determine if the snoop hit a dirty line in the L1 cache.
If CPU BR is asserted during this window, the
MPC2605 will defer to the processor.
Snoop Reads
memory, but allows both the L1 and L2 to keep a valid
copy. In cases where the snoop hits a dirty cache line
in the processor, the MPC2605 will update its contents
as the processor writes the data back to main memory.
MOTOROLA
If transaction one is a cache hit, the MPC2605 will
When a processor brings data into its on-chip cache
Snoops cause the processor and the MPC2605 to
Situations can arise where a cache line is dirty in
A snoop read causes dirty data to be written back to
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is that the DMA bridge can issue a clean transaction
(TT[0:4] = 00000). The other is that the DMA bridge
can do a read transaction (TT[0:4] = x1010). If the
DMA bridge does a read transaction, the MPC2605
determines that it is a snoop read rather than a
processor read by the state of CPU BG the cycle
before TS was asserted. If the processor was not
granted the bus, then the transaction had to have been
issued by the DMA bridge and is, therefore, a snoop
read.
Snoop Writes
back to main memory. The difference from a snoop
read is that the cache line must then be invalidated in
both the processor's cache and in the L2 cache. When
the processor writes data back to memory in response
to a snoop write, the MPC2605 will not cache the data
as it appears on the bus. If a valid copy resides in the
cache, the MPC2605 will invalidate it.
used by the DMA bridge to implement a snoop write.
It can issue a flush transaction (TT[0:4] = 00100), a
read with intent to modify (TT[0:4] = x1110), or a
write with flush (TT[0:4] = 00010). As with snoop
reads, the MPC2605 distinguishes between processor
issued data transactions and snoop transactions by the
state of CPU BG in the cycle previous to the assertion
of TS.
Snoop Kills
immediately invalidated, regardless of whether they
are dirty. This saves time if the DMA operation is
going to modify all the data in the cache line. To
implement a snoop kill, the DMA bridge can issue a
kill transaction (TT[0:4] = 01100) or a write with kill
(TT[0:4] = 00110).
TWO-/FOUR-CHIP IMPLEMENTATION
Multiple Castouts
(COB), it is possible for situations to arise where more
than one device is needed to do a copy-back operation.
Under normal circumstances, each device will enter
castout conditions at different times. In these cases,
when a device determines that it needs to do a castout,
Snoop reads can be implemented in two ways. One
Snoop writes also cause dirty data to be written
Again, there are multiple transactions that can be
Kills are snoops that cause cache entries to be
Because each MPC2605 has its own castout buffer
MPC2605/D
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