MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 14

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

MPC2605/D
2-1-1-1 response. However, even though the
MPC2605 has this ability, it is dependent on the
system to allow this quick of a response to occur. As
discussed above, a data tenure cannot start until the
master has been given a qualified bus grant. In order
for the data tenure to start the cycle after TS is
asserted, the data bus must be granted in the cycle
coinciding with the assertion of TS. At bus speeds of
66 MHz, it is extremely difficult for an arbiter to
detect an assertion of TS and itself assert CPU DBG in
the same cycle. In order to realistically allow this
situation to occur, CPU DBG must be asserted
independent of the processor's assertion of TS.
processor always has a qualified data bus grant when
the data bus is idle. It is also a requirement for systems
that seek to take advantage of the 2-1-1-1 response
time capabilities of the MPC2605. This feature is
typically present in arbiters that have the level of
sophistication necessary to support data streaming.
But it is also a feature of systems that do not even have
a data bus arbiter. In these systems, the data bus grant
of every device in the system is tied to ground. The
assertion of DBB by the current data bus master
effectively removes the qualified data bus grant of all
devices in the system, including its own. Note that in
systems that have no data bus arbiter, it is impossible
to take advantage of data streaming.
parking. Care must be taken when using data bus
parking along with Fast L2 mode. In normal bus mode
when the processor reads data off the bus, it will wait
one cycle before passing the data on to internal
functional units. The purpose of this one cycle waiting
period is to check for an assertion of DRTRY that
invalidates the data that has been previously read. One
of the advantages of running the processor in Fast L2
mode is that this internal processor wait state is
removed.
given data the cycle after TS is asserted, as is possible
with the MPC2605, and the transaction is aborted by
some other device asserting ARTRY. Because the
processor will not sample ARTRY until two cycles
after the assertion of TS, the data read off the bus will
have already been forwarded to the internal functional
units. Thus, incorrect results may occur in the system.
Fast L2 mode with the data bus parked, there must be a
guarantee that ARTRY will never be asserted for cache
14
Data bus parking is a system feature, whereby the
There is another caveat associated with data bus
A problem will arise, however, if the processor is
To avoid this situation in a system that seeks to run
Integrated Secondary Cache for Microprocessors
Freescale Semiconductor, Inc.
For More Information On This Product,
That Implement PowerPC Architecture
Go to: www.freescale.com
read hits. This is a further requirement to be imposed
on the DMA bridge and the memory controller. If this
guarantee cannot be made, the data bus cannot be
parked when running in Fast L2 mode.
Processor Reads
MPC2605 does a tag lookup to determine if this data is
in the cache. If there is a cache hit and CI is not
asserted, the MPC2605 will assert L2 CLAIM and
supply the data to the processor when the data tenure
starts.
asserted) and the MPC2605 detects a cache hit to a
non-dirty or clean cache line, the line will be marked
invalid. If the cache-inhibited read hits a dirty line, the
MPC2605 will assert ARTRY and write the dirty line
back to memory.
perform a linefill only if it is a burst read and it is not
marked cache-inhibited. During a linefill, the
MPC2605 stores the data present on the bus as it is
supplied by the memory controller.
Processor Writes
processor writes are almost the same as for processor
reads. There must be a cache hit and CI must not be
asserted. In addition, however, WT must not be
asserted. Single beat writes that are marked either
write-through or cache-inhibited that hit in the cache,
cause the MPC2605 to assert ARTRY and write the
dirty line back to memory.
Transaction Pipelining
only handle one level of pipelining on the bus. Since
the assertion of L2 CLAIM gives it the ability to assert
AACK, the MPC2605 has the ability to control this
pipeline depth for transactions that are cache hits by
delaying its assertion of AACK.
cache but occur while there is still an outstanding data
transaction on the bus. The timing of the assertion of
AACK for a pipelined cache hit is dependent on the
completion of the previous transaction. For
explanation purposes, the previous transaction will be
referred to as transaction one. The pipelined cache hit
will be referred to as transaction two.
When the processor issues a read transaction, the
If the processor issues a cache-inhibited read (CI
If the read misses in the cache, the MPC2605 will
The conditions for asserting L2 CLAIM for
As explained in Pipeline Depth, the MPC2605 can
Pipelined cache hits are transactions that hit in the
MOTOROLA