MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 17

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

edge of HRESET. If WT is asserted at reset, the
MPC2605 will invalidate all cache entries when
PWRDN is negated. If WT is negated at reset, the
MPC2605 will leave all cache entries as they were
prior to the assertion of PWRDN. However, in this
situation, the system designer must ensure that no bus
activity occur within 2 microseconds of the negation
of PWRDN.
not disable its internal clock network.
ASYNCHRONOUS SIGNALS
signals. These signals were originally defined in the
PowerPC reference platform (PReP) specification.
Because these signals are defined to be asynchronous,
the MPC2605 must synchronize them internally. This
process takes eight clock cycles. Thus, to guarantee
recognition by the MPC2605, assertions of any one of
these signals must last a minimum of eight clock
cycles.
L2 FLUSH
initiates an internal sequence that steps through every
cache line present. Valid lines that are clean, are
immediately marked invalid. Valid lines that are dirty,
must be written back to main memory.
still monitor all transactions on the bus. Any
transaction that is not a processor burst write will
cause the MPC2605 to assert ARTRY. Burst writes
cause the MPC2605 to do a lookup on the affected
address and mark the line invalid if it is present.
transactions, it cannot use the tag RAM for the flush
sequence unless there is a guarantee that no new
transactions will be initiated on the bus. The only way
to ensure that no new transactions will occur is for the
MPC2605 to be granted the bus. Thus, on entering the
sequence initiated by the assertion of L2 FLUSH, the
MPC2605 will assert L2 BR. As soon as L2 BG is
asserted, the MPC2605 can start stepping through the
tag RAM entries.
sequence to complete. Once started, the sequence will
run to completion unless overridden by an assertion of
HRESET.
MOTOROLA
Note: While in the sleep state, the MPC2605 does
The MPC2605 supports four asynchronous control
When L2 FLUSH is asserted, the MPC2605
To keep memory up-to-date, the MPC2605 must
Because the MPC2605 must still monitor all
L2 FLUSH need not be held asserted for the flush
Integrated Secondary Cache for Microprocessors
Freescale Semiconductor, Inc.
For More Information On This Product,
That Implement PowerPC Architecture
Go to: www.freescale.com
L2 MISS INH
not load any new data into the cache. The data already
present will remain valid and the MPC2605 will
respond to cache hits. This condition only lasts as long
as L2 MISS INH is asserted. When L2 MISS INH is
negated, the MPC2605 will start to bring new data into
the cache when there are cache misses.
L2 TAG CLR
invalidate all entries in the cache. This internal
sequence is the same as the one initiated by an
assertion of HRESET. During this sequence, the
MPC2605 will not participate in any bus transaction.
However, it will keep track of all bus transactions so
that when the sequence is finished, the MPC2605 can
immediately participate in the next bus transaction.
assertion of L2 TAG CLR need not be held for the
duration of the sequence. Once asserted, the sequence
will run to completion regardless of the state of
L2 TAG CLR.
L2 UPDATE INH
is disabled from responding to cacheable transactions.
Bus transactions continue to be monitored so that as
soon as L2 UPDATE INH is negated, the MPC204GA
can participate in the next transaction.
When L2 MISS INH is asserted, the MPC2605 will
When L2 TAG CLR is asserted, the MPC2605 will
As is the case with assertions of L2 FLUSH, an
When L2 UPDATE INH is asserted, the MPC2605
MPC2605/D
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