MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 4

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

MPC2605/D
PIN DESCRIPTIONS
4
19G, 17H – 19H, 17J – 19J,
18T, 19T, 18U, 19U, 18V,
17M – 19M, 17N – 19N,
17P – 19P, 17R – 19R,
17K – 19K, 17L – 19L,
17C – 19C, 17D*
Pin Locations
19V, 18W *
19B
18E
17E
3G
1G
2G
3M
2M
2A
2U
2V
1V
2B
3E
1B
2H
1T
AP0 – AP3
Integrated Secondary Cache for Microprocessors
Pin Name
CPU2 BG
CPU3 BG
CPU4 BG
A0 – A31
CPU BG
CPU BR
Freescale Semiconductor, Inc.
ARTRY
AACK
APEN
CFG0
CFG1
CFG2
CFG3
CFG4
ABB
APE
CLK
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Type
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
Address inputs from processor. Can also be outputs for processor
snoop addresses. A0 is the MSB. A31 is the LSB.
Address acknowledge input/output.
Used as an input to qualify bus grants. Driven as an output during
address tenure initiated by the MPC2605.
Address parity.
Address parity error. When an address parity error is detected, APE
will be driven low one clock cycle after the assertion of TS then
High-Z following clock cycle.
Address parity enable. When tied low, enables address parity bits
and the address parity error bit.
Address retry status I/O. Generated when a read or write snoop to a
dirty processor cache line has occurred.
Configuration inputs. These must be tied to either V
CFG0
CFG3
CFG4
Cache inhibit I/O.
Clock input. This must be the same as the processor clock input.
CPU bus grant input.
MPC2605 logically ORs this signal with CPU BG. Used in
multiprocessor configuration as the second CPU BG.
MPC2605 logically ORs this signal with CPU BG. Used in
multiprocessor configuration as the third CPU BG.
MPC2605 logically ORs this signal with CPU BG. Used in
multiprocessor configuration as the fourth CPU BG.
CPU bus request input.
0
0
0
1
1
1
1
CFG1
0
1
1
0
0
1
1
Snoop Data Tenure Selector
1
0
AACK Driver Enable
0
1
Any snoop cycle is address only,
even when TT3 = 1
TT3 will decide whether a snoop
is a data- or address-only tenure
Disable AACK driver
Enable AACK driver
CFG2
0
0
1
0
1
0
1
Description
256KB
512KB; A26 = 0
512KB; A26 = 1
1MB; A25 – A26 = 00
1MB; A25 – A26 = 01
1MB; A25 – A26 = 10
1MB; A25 – A26 = 11
DD
MOTOROLA
or V
SS
.