FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 142

• Manufacturer Part Number: FDC37C665GT-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

nADDRSTB
IOCHRDY
1.
SD<7:0>
PD<7:0>
A0-A10
nDATAST
nWRITE
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
nWAIT
t1
t2
t3
t4
t5
t6
t7
t8
t9
WAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it
does not transition for a minimum of 50 nsec.
PDIR
nIOW
nIOW Asserted to PDATA Valid
nWAIT Asserted to nWRITE Change
nWRITE to Command Asserted
nWAIT Deasserted to Command Deasserted
nWAIT Asserted to PDATA Invalid
Time Out
Command Deasserted to nWAIT Asserted
SDATA Valid to nIOW Asserted
nIOW Deasserted to DATA Invalid
nIOW Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
IOCHRDY Deasserted to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
nWAIT Asserted to Command Asserted
Command Asserted to nWAIT Deasserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
nIOW Deasserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to nWRITE Asserted
nWAIT Asserted to PDIR Low
PDIR Low to nWRITE Asserted
FIGURE 13 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE
t21
t17
t8
t20
t22
t13
t1
Parameter
t14
t10
t3
t16
t6
142
t15
min
60
60
10
10
60
10
60
10
40
10
40
60
0
5
0
0
0
0
0
0
0
0
t11
max
185
190
160
210
185
50
35
12
24
70
10
t4
t12
t7
units
t18
t9
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
t19
t2
t5
Notes
1
1
1
1
1
1