FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 17

• Manufacturer Part Number: FDC37C665GT-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

PIN NO.
22
58
20
21
IDE Data Bit 7
Power Good
nGame Port
Chip Select
CLOCK 1
CLOCK 2
NAME
DESCRIPTION OF PIN FUNCTIONS
IDED7
PWRGD
nGAMECS
PADCF
X1/CLK1
X2/CLK2
SYMBOL
MISCELLANEOUS
BUFFER
OCLK
TYPE
I/O24
ICLK
O4
I
I
17
IDE data bit 7 in the AT mode.
transfers data at I/O addresses 1F0H-1F7H
(R/W), 3F6 (R/W), 3F7(W). IDED7 should
be connected to IDE data bit 7.
FDC37C665GT
transferring data bit 7 between the IDE
device and the host.
3F7H, IDED7 is the FDC disk change bit. In
the XT mode, IDE7 is not used.
FDC37C665GT (Motherboard Mode): This
input indicates that the power (V
active. When PWRGD is inactive, all inputs
to the FDC37C665GT are disconnected and
put in a low power mode, all outputs are put
into high impedance.
registers are preserved as long as V
valid value. The driver current drain in this
mode drops to ISTBY - standby current.
This input has a weak pullup resistor to V
FDC37C666GT (Adapter Mode): This is the
Game Port Chip Select output - active low.
It will go active when the I/O address is
201H.
FDC37C666GT (Adapter Mode): Parallel
Port Mode Control. Refer to FDC37C666GT
hardware
information. Read and latched during reset
active.
The external connection for a parallel
resonant 24 MHz crystal.
compatible oscillator is required if crystal is
not used.
24 MHz crystal. If an external clock is used,
this pin should not be connected. This pin
should not be used to drive any other
drivers.
For device operation, PWRGD must be
configuration
DESCRIPTION
functions
The contents of all
During I/O read of
as
for
CC
A CMOS
a
) is valid.
CC
IDED7
buffer
has a
more
The
CC
.