FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 150

• Manufacturer Part Number: FDC37C665GT-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

PDATA<7:0>
nAUTOFD
1. Maximum value only applies if there is room in the FIFO and a terminal count has not
2. nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to
nACK
t1
t2
t3
t4
t5
t6
been received. ECP can stall by keeping nAUTOFD low.
130 ns.
PDATA Valid to nACK Asserted
nAUTOFD Deasserted to PDATA
Changed
nACK Asserted to nAUTOFD
Deasserted
nACK Deasserted to nAUTOFD
Asserted
nAUTOFD Asserted to nACK Asserted
nAUTOFD Deasserted to nACK
Deasserted
FIGURE 19 - ECP PARALLEL PORT REVERSE TIMING
Parameter
t4
t1
t5
150
t3
t6
min
80
80
0
0
0
0
t4
max
200
200
t2
units
ns
ns
ns
ns
ns
ns
Notes
1,2
2