FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 145

• Manufacturer Part Number: FDC37C665GT-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

1. WRITE is controlled by clearing the PDIR bit to "0" in the control register before
2. This number is only valid if WAIT is active when IOW goes active.
t10
t11
t12
t13
t16
t17
t18
t19
t20
t21
performing an EPP Write.
nADDRSTB
t1
t2
t3
t4
t5
t6
t8
t9
IOCHRDY
nDATAST
PD<7:0>
SD<7:0>
nWRITE
A0-A10
nWAIT
nIOW
PDIR
nIOW Asserted to PDATA Valid
Command Dessserted to nWRITE Change
nWRITE to Command
nIOW Deasserted to Command Deasserted
Command Deasserted to PDATA Invalid
Time Out
SDATA Valid to nIOW Asserted
nIOW Deasserted to DATA Invalid
nIOW Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
IOCHRDY Deasserted to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
nIOW Deasserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to nWAIT Deasserted
FIGURE 15 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE
Parameter
t17
t8
t13
t1
t20
t10
t16
t3
145
t6
min
100
50
10
10
10
10
40
10
0
0
5
0
0
0
0
t11
max
t12
50
40
35
50
12
24
40
50
35
45
t18
t9
t4
t19
units
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
t2
t5
t21
Notes
2