FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 329

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

9.1.20
9.1.21
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: Software clears set bits in this register by writing a 1 to the bit position.
D31_ERR_STS—Device 31 Error Status Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
This register configures the ICH5’s Device 31 responses to various system errors. The actual
assertion of SERR# is enabled via the PCI Command register.
PCI_DMA_CFG—PCI DMA Configuration Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
15:14
13:12
11:10
Bit
7:3
Bit
9:8
7:6
5:4
3:2
1:0
2
1
0
Reserved
SERR# Due to Received Target Abort (SERR_RTA) — R/WC.
0 = Target abort not received.
1 = The Intel
SERR# Due to Delayed Transaction Timeout (SERR_DTT) — R/WC.
0 = PCI master does not violate return for data time described below.
1 = When a PCI master does not return for the data within 1 ms of the cycle’s completion, the ICH5
Reserved
Channel 7 Select — R/W.
00 = Reserved
01 = PC/PCI DMA
10 = Reserved
11 = LPC I/F DMA
Channel 6 Select — R/W. Same bit decode as for channel 7
Channel 5 Select — R/W. Same bit decode as for channel 7
Reserved
Channel 3 Select — R/W. Same bit decode as for channel 7
Channel 2 Select — R/W. Same bit decode as for channel 7
Channel 1 Select — R/W. Same bit decode as for channel 7
Channel 0 Select — R/W. Same bit decode as for channel 7
generates a SERR# when SERR_RTA is set.
clears the delayed transaction and sets this bit. If both SERR_DTT_EN and SERR_EN are set,
then ICH5 also generates an SERR# when SERR_DTT is set.
8Ah
00h
No
90h
0000h
No
®
ICH5 sets this bit when it receives a target abort. If SERR_EN, the ICH5 also
–
91h
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/WC
8 bit
Core
R/W
16 bit
Core
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