FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 61

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

2.13
2.14
Intel
®
Table 14. Processor Interface Signals (Sheet 2 of 2)
Table 15. SM Bus Interface Signals
Table 16. System Management Interface Signals
82801EB ICH5 / 82801ER ICH5R Datasheet
SMBus Interface
System Management Interface
CPUPWRGD /
SMBALERT#/
LINKALERT#
SMLINK[1:0]
INTRUDER#
SMBDATA
A20GATE
SMBCLK
GPIO49
GPIO11
RCIN#
Name
Name
Name
Type
OD
Type
Type
I/OD
I/OD
I/OD
I/OD
I
I
I
I
Keyboard Controller Reset CPU: The keyboard controller can generate INIT# to
the processor. This saves the external OR gate with the ICH5’s other sources of
INIT#. When the ICH5 detects the assertion of this signal, INIT# is generated for
16 PCI clocks.
NOTE: The ICH5 will ignore RCIN# assertion during transitions to the S3, S4, and
A20 Gate: A20GATE is from the keyboard controller. The signal acts as an
alternative method to force the A20M# signal active. It saves the external OR gate
needed with various other PCIsets.
CPU Power Good: This signal should be connected to the processor’s PWRGOOD
input. This is an open-drain output signal (external pull-up resistor required) that
represents a logical AND of the ICH5’s PWROK and VRMPWRGD signals.
This signal may optionally be configured as a GPO.
SMBus Data: External pull-up is required.
SMBus Clock: External pull-up is required.
SMBus Alert: This signal is used to wake the system or generate SMI#. If not used
for SMBALERT#, it can be used as a GPI.
Intruder Detect: This signal can be set to disable system if box detected open.
This signal’s status is readable, so it can be used like a GPI if the Intruder Detection
is not needed.
System Management Link: SMBus link to optional external system management
ASIC or LAN controller. External pull-ups are required. Note that SMLINK0
corresponds to an SMBus Clock signal, and SMLINK1 corresponds to an SMBus
Data signal.
SMLink Alert: This signal is an output from the Intel
ASF or an external management controller in order for the LAN’s SMLINK slave to
be serviced.
S5 states.
Description
Description
Description
®
ICH5 to either the integrated
Signal Description
61