FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 337

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

9.1.29
9.1.30
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
LPC_EN—LPC I/F Enables Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
15:14
15:7
Bit
6:1
Bit
13
12
11
10
0
9
8
Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is aligned on a
128-byte boundary, and must have address lines 31:16 as 0.
Note that this generic decode is for I/O addresses only, not memory addresses. The size of this
range is 128 bytes.
Reserved
Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 = Disable
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
Reserved
CNF2_LPC_EN — R/W.
0 = Disable
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used
CNF1_LPC_EN — R/W.
0 = Disable
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used
MC_LPC_EN — R/W.
0 = Disable
1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used
KBC_LPC_EN — R/W.
0 = Disable
1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used
GAMEH_LPC_EN — R/W.
0 = Disable
1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is
GAMEL_LPC_EN — R/W.
0 = Disable
1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is
for a microcontroller.
for Super I/O devices.
for a microcontroller.
for a microcontroller.
used for a gameport.
used for a gameport.
E4h
0000h
Yes
E6h
00h
Yes
–
–
E5h
E7h
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
16 bit
Core
R/W
16 bit
Core
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