FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 611

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 186. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 2 of 2)
82801EB ICH5 / 82801ER ICH5R Datasheet
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment
2. See the AT Attachment
Sym
t96a
t96b
t98a
t98b
t93
t94
t95
t97
t99
(ATA/ATAPI
measuring these timing parameters.
STROBE output released-to-
driving to the first transition of
critical timing (Tzfs)
Data Output Released-to-Driving
Until the First Tunisian of Critical
Timing (Tdzfs)
Unlimited Interlock Time (Tui)
Maximum time allowed for output
drivers to release (from asserted
or negated) (Taz)
Minimum time for drivers to assert
or negate (from released) (Tzad)
Ready-to-final-STROBE time (no
STROBE edges shall be sent this
long after negation of DMARDY#)
(Trfs)
Maximum time before releasing
IORDY (Tiordyz)
Minimum time before driving
IORDY (see Note 2) (Tziordy)
Time from STROBE edge to
negation of DMARQ or assertion
of STOP (when sender terminates
a burst) (Tss)
–
6) specification name.
Parameter (1)
–
6 with Packet Interface (ATA/ATAPI
Min
70
50
0
0
0
0
Mode 0
(ns)
Max
10
75
20
Min
48
50
0
0
0
0
Mode 1
(ns)
–
6) specification for further details on
Max
10
70
20
Min
31
50
0
0
0
0
Mode 2
Electrical Characteristics
–
(ns)
6 with Packet Interface
Max
10
60
20
Measuring
See Note 2
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Location
Sender
Sender
Sender
Device
Device
Device
Device
Host
14
11
11
11
13
Figure
611