FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 55

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

2.7
Intel
®
Table 9. IDE Interface Signals (Sheet 1 of 2)
82801EB ICH5 / 82801ER ICH5R Datasheet
IDE Interface
PDD[15:0],
PDDACK#,
SDD[15:0]
SDDACK#
PDA[2:0],
PDDREQ,
SDA[2:0]
SDDREQ
PDCS1#,
PDCS3#,
SDCS1#
SDCS3#
Name
Type
I/O
O
O
O
O
I
Primary and Secondary IDE Device Chip Selects for 100 Range: For ATA
command register block. This output signal is connected to the corresponding
signal on the primary or secondary IDE connector.
Primary and Secondary IDE Device Chip Select for 300 Range: For ATA control
register block. This output signal is connected to the corresponding signal on the
primary or secondary IDE connector.
Primary and Secondary IDE Device Address: These output signals are
connected to the corresponding signals on the primary or secondary IDE
connectors. They are used to indicate which byte in either the ATA command block
or control block is being addressed.
Primary and Secondary IDE Device Data: These signals directly drive the
corresponding signals on the primary or secondary IDE connector. There is a weak
internal pull-down resistor on PDD7 and SDD7.
Primary and Secondary IDE Device DMA Request: These input signals are
directly driven from the DRQ signals on the primary or secondary IDE connector. It
is asserted by the IDE device to request a data transfer, and used in conjunction
with the PCI bus master IDE function and are not associated with any AT
compatible DMA channel. There is a weak internal pull-down resistor on these
signals.
Primary and Secondary IDE Device DMA Acknowledge: These signals directly
drive the DAK# signals on the primary and secondary IDE connectors. Each is
asserted by the Intel
transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This
signal is used in conjunction with the PCI bus master IDE function and are not
associated with any AT-compatible DMA channel.
®
ICH5 to indicate to IDE DMA slave devices that a given data
Description
Signal Description
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