FW82801E S L5AW Intel, FW82801E S L5AW Datasheet - Page 26

• Manufacturer Part Number: FW82801E S L5AW
• Manufacturer: Intel

Specifications of FW82801E S L5AW

• Lead Free Status / RoHS Status: Not Compliant

Intel
26
Table 6.
®
82801E C-ICH
82801E C-ICH Signal Description (Sheet 2 of 11)
CPUPWRGD
EE0_SHCLK
EE1_SHCLK
EE0_DOUT
EE1_DOUT
C/BE[3:0]#
CPUSLP#
DEVSEL#
EE0_DIN
EE1_DIN
(HLCLK)
EE0_CS
EE1_CS
CLK14
CLK48
CLK66
Signal
Type
OD
I/O
I/O
O
O
O
O
I
I
I
I
Bus Command and Byte Enables: The command and byte enable signals
are multiplexed on the same PCI pins. During the address phase of a
transaction, C/BE[3:0]# define the bus command. During the data phase,
C/BE[3:0]# define the Byte Enables.
All command encodings not shown are reserved. The 82801E C-ICH does
not decode reserved values, and therefore will not respond when a PCI
master generates a cycle using one of the reserved values.
As a target, the 82801E C-ICH can support DAC mode addressing for 44 bits.
Oscillator Clock: CLK14 is used for 8254 timers and runs at 14.31818 MHz.
48 MHz Clock: CLK48 is used to for the USB controller and runs at 48 MHz.
66 MHz Clock (HLCLK): CLK66 is used for the hub interface and runs at
66 MHz.
Processor Power Good: This signal should be connected to the processor’s
PWRGOOD input. This is an open-drain output signal (external pull-up
resistor required) that represents a logical AND of the 82801E C-ICH’s
PWROK and VRMPWRGD signals.
Processor Sleep: This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during that time,
no snoops occur.
NOTE: The 82801E C-ICH does not support Sleep states. This signal must
Device Select: The 82801E C-ICH asserts DEVSEL# to claim a PCI
transaction. As an output, the 82801E C-ICH asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal 82801E C-ICH address
or an address destined for the hub interface (main memory or AGP). As an
input, DEVSEL# indicates the response to an 82801E C-ICH-initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of
PCIRST#. DEVSEL# remains tri-stated by the 82801E C-ICH until driven by a
target device.
EEPROM Chip Select: These signals are chip-select signals to the
EEPROMs.
EEPROM Data In: These signals transfer data from the EEPROMs to the
82801E C-ICH. These signals have an integrated pull-up resistor.
EEPROM Data Out: These signals transfer data from the 82801E C-ICH to
the EEPROMs.
EEPROM Shift Clock: These signals are the serial shift clock output to the
EEPROMs.
C/BE[3:0]#
0000
0001
0010
0011
0110
0111
1010
1011
1100
1101
1110
1111
be pulled up through an 8.2 K
Command Type
Memory Read Line
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
DAC Mode Address to be latched (target only)
Memory Write and Invalidate
Description
Advance Information Datasheet
resistor to 3.3 V.