FW82801E S L5AW Intel, FW82801E S L5AW Datasheet - Page 69

• Manufacturer Part Number: FW82801E S L5AW
• Manufacturer: Intel

Specifications of FW82801E S L5AW

• Lead Free Status / RoHS Status: Not Compliant

Advance Information Datasheet
Table 52. UART Timings
Table 53. LPC Timing
Table 54. Miscellaneous Timings
t150a
t150a
t153a
t154a
Sym
t10a
t11a
Sym
Sym
t150
t151
t152
t153
t154
t155
t156
t157
t160
t161
t162
t163
t164
t165
SIU0_TXD, SIU1_TXD Valid Delay from UART_CLK Rising
SIU0_DTR#, SIU0_RTS#, SIU1_DTR#, and SIU1_RTS# Valid
Delay from SIU_LCLK Rising
SIU0_RXD, SIU0_CTS#, SIU0_DSR#, SIU0_DCD#,
SIU0_RI# SIU1_RXD, SIU1_CTS#, SIU1_DSR#,
SIU1_DCD#, and SIU1_RI# Setup Time to SIU_LCLK Rising
SIU0_RXD, SIU0_CTS#, SIU0_DSR#, SIU0_DCD#,
SIU0_RI#, SIU1_RXD, SIU1_CTS#, SIU1_DSR#,
SIU1_DCD#, and SIU1_RI# Hold Time from SIU_LCLK Rising
SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI#,
SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI#
high time
SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI#,
SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI#
low time
LAD[3:0] Valid Delay from PCICLK Rising
LAD[3:0] Output Enable Delay from PCICLK Rising
LAD[3:0] Float Delay from PCICLK Rising
LAD[3:0] Setup Time to PCICLK Rising
LAD[3:0] Hold Time from PCICLK Rising
LDRQ[1:0]# Setup Time to PCICLK Rising
LDRQ[1:0]# Hold Time from PCICLK Rising
LFRAME# Valid Delay from PCICLK Rising
SERIRQ Setup Time to PCICLK Rising
SERIRQ Hold Time from PCICLK Rising
RI#, EXTSMI#, GPI, USB Resume Pulse Width
SPKR Valid Delay from OSC Rising
SERR# Active to NMI Active
IGNNE# Inactive from FERR# Inactive
Parameter
Parameter
Parameter
Min
7
0
2
Min
12
2
2
7
0
0
2
Max
200
200
230
Min
100
100
Max
2
2
7
0
11
28
12
RTCCLK
Max
13
11
Units
Units
ns
ns
ns
ns
ns
Intel
ns
ns
ns
ns
ns
ns
ns
ns
Units Notes
ns
ns
ns
ns
®
82801E C-ICH
Notes
Notes
Fig
Fig
Fig
11
11
13
10
10
14
12
10
11
11
11
11
10
10
11
11
9
9
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