FW82801E S L5AW Intel, FW82801E S L5AW Datasheet - Page 27

• Manufacturer Part Number: FW82801E S L5AW
• Manufacturer: Intel

Specifications of FW82801E S L5AW

• Lead Free Status / RoHS Status: Not Compliant

Advance Information Datasheet
Table 6.
82801E C-ICH Signal Description (Sheet 3 of 11)
GPIO[13:12]
GPIO[15:14]
GPIO[17:16]
GPIO[20:18]
GPIO[10:9]
/GPIO[17]#
/LFRAME#
GNT[3:0]#
GPIO[1:0]
GPIO[3:2]
GPIO[5:4]
/LAD[3:0]
/GPIO[16]
/GPIO[17]
FWH[3:0]
/GNT[B]#
/GNT[B]#
FRAME#
/GNT[5]#
GPIO[11]
GPIO[21]
GPIO[22]
GPIO[23]
GNT[A]#
GNT[5]#
GPIO[6]
GPIO[7]
GPIO[8]
FWH[4]
FERR#
Signal
Type
OD
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Numeric Coprocessor Error: This signal is tied to the coprocessor error
signal on the processor. FERR# is only used if the 82801E C-ICH
coprocessor error reporting function is enabled in the General Control
Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is asserted, the
82801E C-ICH generates an internal IRQ13 to its interrupt controller unit. It is
also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to
the processor unless FERR# is active. FERR# requires an external weak
pull-up to ensure a high level when the coprocessor error function is disabled.
Cycle Frame: The current Initiator asserts FRAME# to indicate the beginning
and duration of a PCI transaction. While the initiator asserts FRAME#, data
transfers continue. When the initiator deasserts FRAME#, the transaction is in
the final data phase. FRAME# is an input to the 82801E C-ICH when the
82801E C-ICH is the target, and FRAME# is an output from the 82801E
C-ICH when the 82801E C-ICH is the Initiator. FRAME# remains tri-stated by
the 82801E C-ICH until driven by an Initiator.
Firmware Hub Signals: These signals are muxed with LPC address signals.
Firmware Hub Signals: This signal is muxed with the LPC LFRAME# signal.
PCI Grants: The 82801E C-ICH supports up to four masters on the PCI bus.
GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the other, but
not both). If not needed for PCI or PC/PCI, GNT[5]# can instead be used as a
GPIO.
Pull-up resistors are not required on these signals. If pullups are used, they
should be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an
internal pull-up.
PC/PCI DMA Acknowledges [A:B]: This grant serializes an ISA-like DACK#
for the purpose of running DMA/ISA master cycles over the PCI bus. This is
used by devices such as PCI-based Super I/O or audio codecs which need to
perform legacy 8237 DMA but have no ISA bus.
When not used for PC/PCI, these signals can be used as General Purpose
Outputs. GNTB# can also be used as the fourth PCI bus master grant output.
These signal have internal pull-up resistors.
Fixed as Input only. Main Power Well. Can instead be used for PC/PCI
REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#.
Not implemented.
Fixed as Input only. Main power well. Can be used instead as PIRQ[G:H]#.
Fixed as Input only. Main power well.
Fixed as Input only. Main power well. Not muxed.
Fixed as Input only. Main power well. Not muxed.
Not implemented.
Fixed as Input only. Main power well. Can instead be used for SMBALERT#.
Fixed as Input only. Main power well. Not muxed.
Not implemented.
Fixed as Output only. Main Power Well. Can instead be used for PC/PCI
GNT[A:B]#. GPIO[17] can also alternatively be used for PCI GNT[5]#.
Integrated pull-up resistor.
Fixed as Output only. Main power well.
Fixed as Output only. Main power well.
Fixed as Output only. Main power well. Open-drain output.
Fixed as Output only. Main power well.
Description
Intel
®
82801E C-ICH
27