FW82801E S L5AW Intel, FW82801E S L5AW Datasheet - Page 43

• Manufacturer Part Number: FW82801E S L5AW
• Manufacturer: Intel

Specifications of FW82801E S L5AW

• Lead Free Status / RoHS Status: Not Compliant

3.2.11
Advance Information Datasheet
Table 17. Processor Interface Signals (Sheet 1 of 2)
Processor Interface
CPUSLP#
STPCLK#
IGNNE#
FERR#
A20M#
Name
INIT#
INTR
SMI#
NMI
Type
O
O
O
O
O
O
O
O
I
Mask A20: A20M# goes active based on setting the appropriate bit in the Port 92h
register, or based on the A20GATE signal.
Speed Strap: During the reset sequence, 82801E C-ICH drives A20M# high if the
corresponding bit is set in the FREQ_STRP register.
Processor Sleep: This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during that time, no
snoops occur. The 82801E C-ICH can optionally assert the CPUSLP# signal when
going to the S1 state.
NOTE: The 82801E C-ICH does not support Sleep states. This signal must be
Numeric Coprocessor Error: This signal is tied to the coprocessor error signal
on the processor. FERR# is only used if the 82801E C-ICH coprocessor error
reporting function is enabled in the General Control Register (Device 31:Function
0, Offset D0, bit 13). If FERR# is asserted, the 82801E C-ICH generates an
internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE#
signal to ensure that IGNNE# is not asserted to the processor unless FERR# is
active. FERR# requires an external weak pull-up to ensure a high level when the
coprocessor error function is disabled.
Ignore Numeric Error: This signal is connected to the ignore error pin on the
processor. IGNNE# is only used if the 82801E C-ICH coprocessor error reporting
function is enabled in the General Control Register (Device 31:Function 0, Offset
D0, bit 13). If FERR# is active, indicating a coprocessor error, a write to the
Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE#
remains asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error Register is written, the IGNNE# signal is not asserted.
Speed Strap: During the reset sequence, 82801E C-ICH drives IGNNE# high if
the corresponding bit is set in the FREQ_STRP register.
Initialization: INIT# is asserted by the 82801E C-ICH for 16 PCI clocks to reset
the processor. 82801E C-ICH can be configured to support processor BIST. In that
case, INIT# will be active when PCIRST# is active.
Processor Interrupt: INTR is asserted by the 82801E C-ICH to signal the
processor that an interrupt request is pending and needs to be serviced. It is an
asynchronous output and normally driven low.
Speed Strap: During the reset sequence, 82801E C-ICH drives INTR high if the
corresponding bit is set in the FREQ_STRP register.
Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to the
processor. The 82801E C-ICH can generate an NMI when either SERR# or
IOCHK# is asserted. The processor detects an NMI when it detects a rising edge
on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in
the NMI Status and Control Register.
Speed Strap: During the reset sequence, 82801E C-ICH drives NMI high if the
corresponding bit is set in the FREQ_STRP register.
System Management Interrupt: SMI# is an active low output synchronous to
PCICLK. It is asserted by the 82801E C-ICH in response to one of many enabled
hardware or software events.
Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK.
It is asserted by the 82801E C-ICH in response to one of many hardware or
software events. When the processor samples STPCLK# asserted, it responds by
stopping its internal clock.
pulled up through an 8.2 K
Description
resistor to 3.3 V.
Intel
®
82801E C-ICH
43