FW82801E S L5AW Intel, FW82801E S L5AW Datasheet - Page 28

• Manufacturer Part Number: FW82801E S L5AW
• Manufacturer: Intel

Specifications of FW82801E S L5AW

• Lead Free Status / RoHS Status: Not Compliant

Intel
28
Table 6.
®
82801E C-ICH
82801E C-ICH Signal Description (Sheet 4 of 11)
LAN0_RSTSYNC
LAN1_RSTSYNC
GPIO[28:27]
GPIO[31:29]
INTRUDER#
LAN0_CLK
LAN1_CLK
IRQ[14:15]
/FWH[3:0]
HL_STB#
GPIO[24]
GPIO[25]
GPIO[26]
HLCOMP
HUBREF
LAD[3:0]
HL[11:0]
HL_STB
IGNNE#
Signal
IRDY#
INIT#
INTR
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
Can be input or output. Main power well.
Can be input or output. Main power well. Not Muxed.
Not implemented.
Can be input or output. Main power well. Unmuxed.
Not implemented.
Hub Interface Signals
Hub Interface Strobe: One of two differential strobe signals used to transmit
and receive data through the hub interface.
Hub Interface Strobe Complement: Second of the two differential strobe
signals.
Hub Interface Compensation: Used for hub interface buffer compensation.
0.9 V reference for the hub interface.
Ignore Numeric Error: This signal is connected to the ignore error pin on the
processor. IGNNE# is only used if the 82801E C-ICH coprocessor error
reporting function is enabled in the General Control Register (Device
31:Function 0, Offset D0, bit 13). When FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h) causes the
IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If
FERR# is not asserted when the Coprocessor Error Register is written, the
IGNNE# signal is not asserted.
Speed Strap: During the reset sequence, 82801E C-ICH drives IGNNE# high
if the corresponding bit is set in the FREQ_STRP register.
Initialization: INIT# is asserted by the 82801E C-ICH for 16 PCI clocks to
reset the processor. 82801E C-ICH can be configured to support processor
BIST. In that case, INIT# will be active when PCIRST# is active.
Processor Interrupt: INTR is asserted by the 82801E C-ICH to signal the
processor that an interrupt request is pending and needs to be serviced. It is
an asynchronous output and normally driven low.
Speed Strap: During the reset sequence, 82801E C-ICH drives INTR high if
the corresponding bit is set in the FREQ_STRP register.
Intruder Detect: This signal can be set to disable system if box detected
open. This signal’s status is readable, so it can be used like a GPI if the
Intruder Detection is not needed.
Initiator Ready: IRDY# indicates the 82801E C-ICH's ability, as an Initiator,
to complete the current data phase of the transaction. It is used in conjunction
with TRDY#. A data phase is completed on any clock both IRDY# and TRDY#
are sampled asserted. During a write, IRDY# indicates the 82801E C-ICH has
valid data present on AD[31:0]. During a read, it indicates the 82801E C-ICH
is prepared to latch data. IRDY# is an input to the 82801E C-ICH when the
82801E C-ICH is the Target and an output from the 82801E C-ICH when the
82801E C-ICH is an Initiator. IRDY# remains tri-stated by the 82801E C-ICH
until driven by an Initiator.
Interrupt Request 14:15: These interrupt inputs are connected to the IDE
drives. IRQ14 is used by the drives connected to the primary controller and
IRQ15 is used by the drives connected to the secondary controller.
LPC Multiplexed Command, Address, Data: Internal pull-ups are provided.
LAN Interface Clock: This signal is driven by the LAN Connect component.
The frequency range is 0.8 MHz to 50 MHz.
LAN Reset/Sync: The LAN Connect component’s Reset and Sync signals
are multiplexed onto this pin.
Description
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