FW82801E Intel, FW82801E Datasheet
FW82801E
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FW82801E Summary of contents
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... Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Advance Information Datasheet Two cascaded 8237 DMA controllers ...
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... Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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Contents 1.0 Introduction....................................................................................................................................7 1.1 Overview ............................................................................................................................... 9 1.2 About this Document .......................................................................................................... 10 2.0 Package Information ................................................................................................................... 11 2.1 Ball Location ....................................................................................................................... 11 2.2 Mechanical Specifications .................................................................................................. 23 3.0 Signal Descriptions ..................................................................................................................... 25 3.1 Alphabetical Signal Reference............................................................................................25 3.2 Signals Grouped ...
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... Intel 82801E C-ICH Package (Top View) ................................................................................. 23 ® 5 Intel 82801E C-ICH Package (Side View) ................................................................................ 24 ® 6 Intel 82801E C-ICH Package (Bottom View)............................................................................ 24 7 Required External RTC Circuit ................................................................................................... 50 8 Example V5REF Sequencing Circuit .......................................................................................... 51 9 Clock Timing ............................................................................................................................... 70 10 Valid Delay From Rising Clock Edge.......................................................................................... 70 11 Setup And Hold Times................................................................................................................ 71 12 Float Delay ...
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Tables 1 PCI Devices and Functions ..........................................................................................................9 2 Related Documents ....................................................................................................................10 3 Industry Specifications................................................................................................................ 10 4 Ball List By Number ....................................................................................................................12 5 Ball List By Signal Name ............................................................................................................ 17 6 82801E C-ICH Signal Description .............................................................................................. 25 7 Hub Interface Signals ...
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Contents 50 SMBus Timing ............................................................................................................................ 68 51 SIU LPC and Serial IRQ Timings ............................................................................................... 68 52 UART Timings ............................................................................................................................ 69 53 LPC Timing ................................................................................................................................. 69 54 Miscellaneous Timings ............................................................................................................... 69 55 Power Sequencing and Reset Signal Timings ........................................................................... 70 56 ...
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... Introduction ® The Intel 82801E Communications I/O Controller Hub (82801E C-ICH highly integrated multifunctional communications I/O controller hub that provides the interface to the PCI bus and integrates many of the functions needed in today’s communications applications. This document provides a detailed description of the 82801E C-ICH thermal, electrical and mechanical specifications, including signals, pinout, packaging, electrical characteristics, and testability ...
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... Intel 82801E C-ICH ® Figure 2. Intel 82801E C-ICH Simplified Block Diagram RTCRST# PDD[15:0] SDD[15:0] PDDREQ SDDREQ PDDACK# SDDACK# CPUSLP# STPCLK# A20GATE CPUPWRGD PIRQ[A:F]# PIRQ[G:H]/GPIO[5:4] IRQ[15:14] APICCLK APICD[1:0] GPIO[13:11,8:4,1:0] GPIO[23:16] GPIO[28:27,25:24] EE0_SHCLK EE0_DOUT SIU_LCLK SIU0_RXD SIU0_TXD SIU0_CTS# SIU0_DSR# SIU0_DCD# SIU0_DTR# ...
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... Hub Interface to PCI Bridge PCI to LPC Bridge (includes: DMA, Timers, compatible interrupt controller, APIC, RTC, SIU, processor interface control, power management control, system management control, and GPIO control) IDE Controller USB Controller SMBus Controller LAN0 Controller LAN1 Controller ® Intel 82801E C-ICH C devices 9 ...
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... Firmware Hub (FWH) Datasheet This document assumes a working knowledge of the vocabulary and principles of USB, IDE, SMBus, PCI, LAN, LPC, and serial I/O. Details of these features are described in the Intel 82801E Communications I/O Controller Hub (C-ICH) Developer’s Manual (order number 273599) and in the industry specifications listed in Table 3. ...
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... APICD[0] SPKR PDD[8] PDD[4] PDD[13] PDD[15] PDD[14] NC[3] VSS APICCLK PDD[9] VSS PDDREQ V5REF PDD[11] PDD[ SMLINK ® Intel 82801E C-ICH SIU SIU1_ VSS SIU1_ UART_ VSS SIU0_ LAN1_ VSS RTS# DSR# CLK RI# TXD[1] B ...
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... Intel 82801E C-ICH Table 4. Ball List By Number Ball Number A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B10 B11 B12 B13 B14 B15 B16 B17 B18 ...
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... C/BE[0]# J4 AD[11] J5 Vcc3_3 J6 Vcc3_3 J18 Vcc1_8 J19 Vcc1_8 J20 Vcc1_8 J21 Vcc1_8 J22 Vcc3_3 J23 Vcc3_3 K1 Vcc3_3 K2 Vcc3_3 K3 EE1_CS K4 ® Intel 82801E C-ICH Signal Name EE0_CS Vcc1_8 LAN0_CLK Vcc1_8 SERR# AD[12] VSS AD[3] AD[2] Vcc3_3 Vcc3_3 EE1_DIN EE0_DOUT LAN0_TXD[1] VSS LAN0_RXD[1] C/BE[1]# AD[14] AD[8] AD[1] AD[5] Vcc3_3 Vcc3_3 LAN1_RXD[1] LAN0_RXD[0] ...
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... Intel 82801E C-ICH Table 4. Ball List By Number Ball Number K5 K6 K10 K11 K12 K13 K14 K18 K19 K20 K21 K22 K23 L10 L11 L12 L13 L14 L19 L20 L21 L22 L23 M10 M11 M12 M13 M14 ...
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... INIT# NMI INTR NC[10] USBP1N Vcc3_3 NC[6] V5REF Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 SDDACK# SIORDY (/SDRSTB/ SWDMARDY#) V_CPU_IO CPUPWRGD IGNNE# ® Intel 82801E C-ICH Signal Name W1 USBP1P W2 NC[9] W3 NC[7] W4 OC[1]# W5 VSS W6 VSS W7 NC[1] W8 VccRTC W9 PWROK W10 Vcc3_3 W11 CLK14 ...
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... Intel 82801E C-ICH Table 4. Ball List By Number Ball Number Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 ...
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... GNT[B]#/GNT[5]#/GPIO[17] K1 GPIO[6] D6 GPIO[7] L2 GPIO[8] B4 GPIO[12] L1 GPIO[13] A2 GPIO[18] M1 GPIO[19] C5 GPIO[20] M2 GPIO[21] AC9 GPIO[22] AB9 GPIO[23] Y10 GPIO[24] ® Intel 82801E C-ICH Ball Number W11 AB8 J23 V22 R19 J3 F20 E21 G20 C23 F19 G19 D21 E20 AA9 B1 A8 D10 E8 ...
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... Intel 82801E C-ICH Table 5. Ball List By Signal Name Signal Name GPIO[25] GPIO[27] GPIO[28] HL[0] HL[1] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HL[10] HL[11] HL_STB HL_STB# HLCOMP HUBREF IGNNE# INIT# INTR INTRUDER# IRDY# IRQ[14] IRQ[15] LAD[0]/FWH[0] LAD[1]/FWH[1] LAD[2]/FWH[2] LAD[3]/FWH[3] LAN0_CLK LAN0_RSTSYNC LAN0_RXD[0] LAN0_RXD[1] LAN0_RXD[2] LAN0_TXD[0] LAN0_TXD[1] LAN0_TXD[2] 18 Table 5 ...
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... SDD[14] A7 SDD[15] K5 SDDACK# W9 SDDREQ W23 SDIOR# (/SDWSTB/ B5 SRDMARDY#) D7 SDIOW# (/SDSTOP) E9 SERIRQ M4 SERR# C9 SIORDY (/SDRSTB/ C10 SWDMARDY#) P4 SIU_LAD[0] ® Intel 82801E C-ICH Ball Number AA6 Y7 AA7 AB23 AA21 W20 U19 Y21 Y19 AC21 AC20 AA19 AA18 W16 Y15 AC18 AA17 ...
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... Intel 82801E C-ICH Table 5. Ball List By Signal Name Signal Name SIU_LAD[1] SIU_LAD[2] SIU_LAD[3] SIU_LCLK SIU_LDRQ# SIU_LFRAME# SIU_RESET# SIU_SERIRQ SIU0_CTS# SIU0_DCD# SIU0_DSR# SIU0_DTR# SIU0_RI# SIU0_RTS# SIU0_RXD SIU0_TXD SIU1_CTS# SIU1_DCD# SIU1_DSR# SIU1_DTR# SIU1_RI# SIU1_RTS# SIU1_RXD SIU1_TXD SMBALERT#/GPIO[11] SMBCLK SMBDATA SMI# SMLINK[0] ...
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... U18 VSS V3 VSS V6 VSS V7 VSS V8 VSS V9 VSS V10 VSS V14 VSS V15 VSS V16 VSS V17 VSS V18 VSS ® Intel 82801E C-ICH Ball Number W10 W8 AA8 W21 A13 A17 A20 A23 C4 C6 C12 C19 D1 D9 D22 E5 E7 E15 E19 ...
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... Intel 82801E C-ICH Table 5. Ball List By Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 22 Table 5. Ball List By Signal Name Ball Number ...
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... Mechanical Specifications ® Figure 4. Intel 82801E C-ICH Package (Top View) Notes: 1. All Dimensions and tolerances conform to ANSI Y14.5M - 1982 2. All Dimensions are in millimeters. Advance Information Datasheet ® Intel 82801E C-ICH 23 ...
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... All Dimensions are in millimeters. 3. Primary datum -C- and seating plane are defined by the spherical crowns of the solder balls. ® Figure 6. Intel 82801E C-ICH Package (Bottom View) Notes: 1. All Dimensions and tolerances conform to ANSI Y14.5M - 1982 2. Dimension is measured at the maximum solder ball diameter. ...
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... APIC Clock: The APIC clock runs at 33.333 MHz. APIC Data: These bidirectional open drain signals are used to send and receive data over the APIC bus. As inputs, the data is valid on the rising edge I/OD of APICCLK. As outputs, new data is driven from the rising edge of the APICCLK. ® Intel 82801E C-ICH Description 25 ...
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... Intel 82801E C-ICH Table 6. 82801E C-ICH Signal Description (Sheet 2 of 11) Signal C/BE[3:0]# CLK14 CLK48 CLK66 (HLCLK) CPUPWRGD CPUSLP# DEVSEL# EE0_CS EE1_CS EE0_DIN EE1_DIN EE0_DOUT EE1_DOUT EE0_SHCLK EE1_SHCLK 26 Type Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command ...
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... GNT[A:B]#. GPIO[17] can also alternatively be used for PCI GNT[5]#. Integrated pull-up resistor. O Fixed as Output only. Main power well. O Fixed as Output only. Main power well. OD Fixed as Output only. Main power well. Open-drain output. O Fixed as Output only. Main power well. ® Intel 82801E C-ICH Description 27 ...
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... Intel 82801E C-ICH Table 6. 82801E C-ICH Signal Description (Sheet 4 of 11) Signal GPIO[24] GPIO[25] GPIO[26] GPIO[28:27] GPIO[31:29] HL[11:0] HL_STB HL_STB# HLCOMP HUBREF IGNNE# INIT# INTR INTRUDER# IRDY# IRQ[14:15] LAD[3:0] /FWH[3:0] LAN0_CLK LAN1_CLK LAN0_RSTSYNC LAN1_RSTSYNC 28 Type I/O Can be input or output. Main power well. I/O Can be input or output. Main power well. Not Muxed. ...
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... ATA command block or control block is being addressed. Primary IDE Device Chip Selects for 100 Range: This signal is for the ATA O command register block. This output signal is connected to the corresponding signal on the primary IDE connector. ® Intel 82801E C-ICH Description 29 ...
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... Intel 82801E C-ICH Table 6. 82801E C-ICH Signal Description (Sheet 6 of 11) Signal PDCS3# PDD[15:0] PDDACK# PDDREQ PDIOR# /(PDWSTB /PRDMARDY#) PDIOW# /(PDSTOP) PERR# PIORDY /(PDRSTB /PWDMARDY#) PIRQ[A:D]# 30 Type Primary IDE Device Chip Select for 300 Range: This signal is for the ATA O control register block. This output signal is connected to the corresponding signal on the primary IDE connector ...
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... Crystal Input 1: This signal is connected to the 32.768 KHz crystal Special external crystal is used, then RTCX1 can be driven with the desired clock rate. Crystal Input 2: This signal is connected to the 32.768 KHz crystal Special external crystal is used, then RTCX2 should be left floating. ® Intel 82801E C-ICH Description 31 ...
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... Intel 82801E C-ICH Table 6. 82801E C-ICH Signal Description (Sheet 8 of 11) Signal SDA[2:0] SDCS1# SDCS3# SDD[15:0] SDDACK# SDDREQ SDIOR# /(SDWSTB/ SRDMARDY#) SDIOW# /(SDSTOP) SERIRQ SERR# SIORDY /(SDRSTB /SWDMARDY#) 32 Type Secondary IDE Device Address: These output signals are connected to the corresponding signals on the secondary IDE connectors. They are used to ...
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... Bit 6 is the complement of the RI# signal. Bit 2 (TERI) of the MSR indicates whether the DCD# input has changed state since the previous reading of the MSR. When the RI bit of the MSR changes state an interrupt is generated if the Modem Status Interrupt is enabled. ® Intel 82801E C-ICH Description 33 ...
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... Intel 82801E C-ICH Table 6. 82801E C-ICH Signal Description (Sheet 10 of 11) Signal SIU0_RTS# SIU1_RTS# SIU0_RXD SIU1_RXD SIU0_TXD SIU1_TXD SMBALERT# /GPIO[11] SMBCLK SMBDATA SMI# SMLINK[1:0] SPKR STOP# STPCLK# SUSCLK THRM# TP[3:0] 34 Type Request To Send for UART0 and UART1: When low these pins informs the modem or data set that CICH UART 0, 1 are ready to establish a communication link ...
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... C-ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. VRM Power Good: This can be considered to be the CPU’s VRM power I good. This signal should be ANDed with the ATX power supply’s PWROK signal. Grounds. ® Intel 82801E C-ICH Description 35 ...
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... Intel 82801E C-ICH 3.2 Signals Grouped By Type 3.2.1 Hub Interface to Host Controller Table 7. Hub Interface Signals Name Type HL[11:0] HL_STB HL_STB# HLCOMP 3.2.2 Link to LAN Connect Table 8. LAN Interface Name LAN0_CLK LAN1_CLK LAN0_RSTSYNC LAN1_RSTSYNC LAN0_RXD[2:0] LAN1_RXD[2:0] LAN0_TXD[2:0] LAN1_TXD[2:0] 3.2.3 EEPROM Interface Table 9. EEPROM Interface Name ...
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... AGP input, DEVSEL# indicates the response to an 82801E C-ICH-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the 82801E C-ICH until driven by a target device. ® Intel 82801E C-ICH 37 ...
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... Intel 82801E C-ICH Table 11. PCI Interface Signals (Sheet Name Type FRAME# I/O IRDY# I/O TRDY# I/O STOP# I/O PAR I/O PERR# I/O REQ[3:0]# /REQ[5]# /REQ[B]# /GPIO[1] 38 Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue ...
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... DMA but have no ISA bus. When not used for PC/PCI, these signals can be used as General Purpose Outputs. GNTB# can also be used as the fifth PCI bus master grant output. These signal have internal pull-up resistors. ® Intel 82801E C-ICH Description 39 ...
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... Intel 82801E C-ICH 3.2.6 IDE Interface Table 12. IDE Interface Signals Name PDCS1# SDCS1# PDCS3# SDCS3# PDA[2:0] SDA[2:0] PDD[15:0] SDD[15:0] PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# /(PDWSTB /PRDMARDY#) SDIOR# /(SDWSTB /SRDMARDY#) PDIOW# /(PDSTOP) SDIOW# /(SDSTOP) PIORDY /(PDRSTB /PWDMARDY#) SIORDY /(SDRSTB /SWDMARDY#) 40 Type Primary and Secondary IDE Device Chip Selects for 100 Range: These O signals are for the ATA command register block ...
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... APIC Clock: The APIC clock runs at 33.333 MHz. APIC Data: These bidirectional open drain signals are used to send and receive data over the APIC bus. As inputs, the data is valid on the rising edge I/OD of APICCLK. As outputs, new data is driven from the rising edge of the APICCLK. ® Intel 82801E C-ICH Description 41 ...
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... Intel 82801E C-ICH 3.2.9 USB Interface Table 15. USB Interface Signals Name USBP0P USBP0N USBP1P USBP1N OC[1:0]# 3.2.10 Power Signals Table 16. Power Signals Name Type PWROK RSM_PWROK RSMRST# VRMPWRGD 42 Type Universal Serial Bus Port 1:0 Differential: These differential pairs are used to I/O transmit Data/Address/Command signals for ports 0 and 1. ...
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... Stop Clock Request: STPCLK active low output synchronous to PCICLK asserted by the 82801E C-ICH in response to one of many hardware or O software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock. ® Intel 82801E C-ICH Description resistor to 3 ...
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... Intel 82801E C-ICH Table 17. Processor Interface Signals (Sheet Name Type RCIN# A20GATE CPUPWRGD OD 3.2.12 SMBus Interface Table 18. SMBus Interface Signals Name Type SMBDATA I/OD SMBCLK I/OD SMBALERT# /GPIO[11] 3.2.13 System Management Interface Table 19. System Management Interface Signals Name Type INTRUDER# SMLINK[1:0] I/OD 3.2.14 Real Time Clock Interface Table 20 ...
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... The DTR#x(x=0,1) output signals can be set to an active O low by programming the DTRx (x-0,1) (bit0) of the Modem control register to a logic ‘1’. A Reset operation sets this signal to its inactive state (logic ‘1’). LOOP mode operation holds this signal in its inactive state. ® Intel 82801E C-ICH Description Description 45 ...
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... Intel 82801E C-ICH Table 22. Universal Asynchronous Receive And Transmit (UART 0, 1) (Sheet Signal Name SIU0_RI# SIU1_RI# SIU0_RTS# SIU1_RTS# SIU0_RXD SIU1_RXD SIU0_TXD SIU1_TXD 3.2.17 SIU LPC Interface Table 23. SIU Interface Signal Name Type SIU_LAD[3:0] I/O SIU_LCLK SIU_LDRQ# SIU_LFRAME# SIU_RESET# SIU_SERIRQ I/O 46 Type Ring Indicator for UART0 and UART1: Active low, this pin indicates that a telephone ringing signal has been received by the external agent ...
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... Not implemented. I/O Can be input or output. Main power well. Not Muxed. I/O Can be input or output. Main power well. O Fixed as Output only. Main power well. OD Fixed as Output only. Main power well. Open-drain output. ® Intel 82801E C-ICH Description . Used for NAND Used for NAND SS . ...
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... Intel 82801E C-ICH Table 25. General Purpose I/O Signals (Sheet Name Type GPIO[21] GPIO[20:18] GPIO[17:16] GPIO[15:14] GPIO[13:12] GPIO[11] GPIO[10:9] GPIO[8] GPIO[7] GPIO[6] GPIO[5:4] GPIO[3:2] GPIO[1:0] 3.2.20 Power and Ground Table 26. Power and Ground Signals Name HUBREF 0.9 V reference for the hub interface. V5REF Reference for 5 V tolerance on Core well inputs ...
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... TCO Timer system reboot feature). The status of this strap PWROK is readable via the NO_REBOOT bit (bit 1, D31: F0, Offset D4h). < ® Intel 82801E C-ICH Comment Test Mode No Test Mode Selected XOR Chain 1 XOR Chain 2 XOR Chain 3 XOR Chain 4 ...
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... Intel 82801E C-ICH Table 28. Test Mode Selection Number of PCI Clocks RTCRST# driven low after PWROK active 3.3.2.2 Test Straps • The 82801E C-ICH’s TP[0] (Test Point) signal must be pulled to Vcc3_3 with an external pull-up resistor. • The 82801E C-ICH’s TP[1] must be routed to a test point with an option to jumper to Vcc1_8. ...
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... V_CPU_IO: Powered by the main power supply via processor voltage regulator. VccRTC: When other power is available (from the main supply), external diode coupling will provide power to reduce the drain on the RTC battery. Assumed to operate from 3.3 V down to 2.0 V. ® Intel 82801E C-ICH 5V Supply 1k To System ...
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... Intel 82801E C-ICH 3.4.2 Integrated Pull-Ups and Pull-Downs Table 30. Integrated Pull-Up and Pull-Down Resistors Signal EE0_DIN, EE1_DIN EE0_DOUT, EE1_DOUT GNT[A:B]#/GNT[5]#/GPIO[17:16] LAD[3:0]#/FWH[3:0]# LDRQ[1:0] SPKR LAN0_RXD[2:0], LAN1_RXD[2:0] PDD[7]/SDD[7] PDDREQ/SDDREQ NOTES: 1. Simulation data shows that these resistor values can range from ...
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... RSMRST# Main I/O PCIRST# Main I/O PCIRST# Main I/O PCIRST# LPC Interface Main I/O PCIRST# Main I/O PCIRST# LAN Connect and EEPROM Interface LAN I/O RSM_PWROK ® Intel 82801E C-ICH Immediately During Reset after Reset High-Z Undefined High-Z Undefined High-Z High-Z High-Z High-Z High High High-Z High ...
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... Intel 82801E C-ICH Table 32. Power Plane and States for Output and I/O Signals (Sheet Signal Name EE0_DOUT, EE1_DOUT EE0_SHCLK, EE1_SHCLK LAN0_RSTSYNC, LAN1_RSTSYNC LAN0_TXD[2:0], LAN1_TXD[2:0] PDA[2:0], SDA[2:0] PDCS1#, PDCS3# PDD[15:0], SDD[15:0] PDDACK#, SDDACK# PDIOR#, PDIOW# SDCS1#, SDCS3# SDIOR#, SDIOW# PIRQ[A:H]# SERIRQ ...
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... Main I/O PCIRST# Main I/O PCIRST# Main I/O PCIRST# Main I/O PCIRST# Main I/O PCIRST# Main I/O RSMRST# Main I/O RSMRST# Main I/O RSMRST# ® Intel 82801E C-ICH Immediately During Reset after Reset High High High-Z High-Z High-Z High-Z High-Z with Low internal pull-up Running High See Note 2 High ...
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... Intel 82801E C-ICH Table 33. Power Plane for Input Signals Signal Name A20GATE APICCLK CLK14 CLK48 CLK66 EE0_DIN, EE1_DIN FERR# INTRUDER# IRQ[15:14] LAN0_CLK, LAN1_CLK RSM_PWROK LAN0_RXD[2:0], LAN1_RXD[2:0] LDRQ[0]# LDRQ[1]# OC[1:0]# PCICLK PDDREQ PIORDY PWROK RCIN# REQ[3:0]#, REQ[5]# REQ[B:A]# RI# RSMRST# RTCRST# SDDREQ SERR# ...
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... Electrical Characteristics Note: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. 4.1 Absolute Maximum Ratings Table 34 ...
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... Intel 82801E C-ICH 4.3 DC Characteristics Table 36. 82801E C-ICH Power Consumption Measurements Power Plane 1.8 V Core 3.3 V I/O 1.8 V LAN 3.3 V LAN (LAN+LAN Connect Component) Table 37. DC Characteristic Input Signal Association Symbol V /V IH1 IL1 (5 V Tolerant IH2 IL2 V /V IH3 IL3 V /V IH4 IL4 ...
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... SDDACK#, PDA[2:0], SDA[2:0], PDCS[3,1]#, SDCS[3,1]# Processor Signals: A20M#, CPUPWRGD, CPUSLP#, IGNNE#, INIT#, INTR, NMI, SMI#, STPCLK# PCI Signals: AD[31:0], C/BE[3:0]#, PCIRST#, GNT[5, 3:0]#, PAR, DEVSEL#, PERR#, PLOCK#, STOP#, TRDY#, IRDY#, FRAME#, SERR# Interrupt Signals: SERIRQ, PIRQ[A:F]#, PIRQ[G:H]#/GPIO[5:4] ® Intel 82801E C-ICH Max Unit Notes 0.8 V V5REF + 0 ...
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... Intel 82801E C-ICH Table 39. DC Characteristic Output Signal Association (Sheet Symbol V /V OH4 OL4 V /V OL5 OH5 V /V OL6 OH6 V /V OL7 OH7 V /V OL8 OH8 Table 40. DC Output Characteristics Symbol Parameter V Output Low Voltage OL1 V Output High Voltage ...
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... C L Crystal Load Capacitance NOTES: 1. Includes APICCLK, CLK14, CLK48, CLK66, LAN_CLK and PCICLK Advance Information Datasheet Parameter Min. 4.75 3.102 1.7 0.48 (Vcc1.8) 0.52 (Vcc1.8) 0.64 (Vcc1.8) 0.70 (Vcc1.8) 2.0 1.9 0.2 0.8 1.3 0.8 -1.0 -10 -100 ® Intel 82801E C-ICH Max Unit Notes 5.25 V 3.498 V 1 Normal Mode V Enhanced Mode 3.6 V Applied to V USBP[1:0][P:N] Applied to 1.3 ...
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... Intel 82801E C-ICH 4.4 AC Characteristics Table 42. Clock Timings (Sheet Sym t1 Period t2 High Time t3 Low Time t4 Rise Time t5 Fall Time t6 Period t7 High Time t8 Low time f clk48 Operating Frequency t9 Frequency Tolerance t10 High Time t11 Low time t12 Rise Time t13 Fall Time ...
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... PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output Enable Delay from PCICLK Rising Advance Information Datasheet Parameter Min 12 12 1.0 1.0 Hub Interface Clock 6.0 6.0 0.25 0.25 1.0 Parameter Min 14.7456 2500 7 7 Parameter ® Intel 82801E C-ICH Max Unit Notes Figure 5 5 ...
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... Intel 82801E C-ICH Table 44. PCI Interface Timing (Sheet Sym C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, t45 PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, t46 SERR#, PERR#, DEVSEL#, Setup Time to PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, ...
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... The specification symbols in parentheses correspond to the Ultra ATA specification name. Advance Information Datasheet Parameter Mode 0 (ns) Parameter (1) Min Max 240 112 230 150 160 20 ® Intel 82801E C-ICH Min Max Units Notes Figure 2,3 15, 16 3,4 15, 16 Mode 1 (ns) Mode 2 (ns) Figure Min Max Min Max 160 ...
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... Intel 82801E C-ICH Table 47. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) Sym t80 Sustained Cycle Time (T2cyctyp) Cycle Time (Tcyc) (2) t81 t82 Two Cycle Time (T2cyc) t83 Data Setup Time (Tds) t84 Data Hold Time (Tdh) t85 Data Valid Setup Time (Tdvs) ...
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... Parameter Min Full Speed Source (Note -3.5 -4 160 -2 -18 Low Speed Source (Note -25 -14 1.25 -40 -152 -200 670 ® Intel 82801E C-ICH Max Units Notes Fig 3 175 ...
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... Intel 82801E C-ICH Table 49. IOAPIC Bus Timing Sym t120 APICCD[1:0]# Valid Delay from APICCLK Rising t121 APICCD[1:0]# Setup Time to APICCLK Rising t122 APICCD[1:0]# Hold Time from APICCLK Rising Table 50. SMBus Timing Sym t130 Bus Tree Time Between Stop and Start Condition Hold Time after (repeated) Start Condition ...
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... SPKR Valid Delay from OSC Rising t164 SERR# Active to NMI Active t165 IGNNE# Inactive from FERR# Inactive Advance Information Datasheet Parameter Parameter Min Parameter Min ® Intel 82801E C-ICH Min Max Units Notes Fig 100 9 ...
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... Intel 82801E C-ICH Table 55. Power Sequencing and Reset Signal Timings Sym t170 VccRTC active to RTCRST# inactive t171 VccRTC supply active to Vcc supplies active t172 V5Ref active to Vcc3_3, Vcc1_8 active Vcc supplies active to PWROK, VRMPWRGD t173 active t174 AC_RST# active low pulse width ...
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... Figure 11. Setup And Hold Times Clock Input Figure 12. Float Delay Input Output Figure 13. Pulse Width Figure 14. Output Enable Delay Clock Output Advance Information Datasheet 1.5V Setup Time Hold Time Float Delay Pulse Width VT VT 1.5V Output Enable Delay VT ® Intel 82801E C-ICH 71 ...
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... Intel 82801E C-ICH Figure 15. IDE PIO Mode DA[2:0], CS1#, CS3# Figure 16. IDE Multiword DMA CLK66 t67 DDREQ[1:0] DDACK[1:0] DIOx# DD[15:0] Read DD[15:0] Write 72 CLK66 t60 DIOx# t69 DD[15:0] Write DD[15:0] Read IORDY t62,t63 t65 t60 t61 t75 t70 t71 Read Data t69 t69 Write Data ...
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... DMARDY# (host) STROBE (drive) DD[15:0] DA[2:0], CS[1:0] Figure 18. Ultra ATA Mode (Sustained Burst) STROBE @ sender Data @ sender STROBE @ receiver Data @ receiver Advance Information Datasheet t91 t89 t89 t82 t81 t85 t86 t86 t83 t84 t84 ® Intel 82801E C-ICH t81 t85 t86 t83 t84 73 ...
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... Intel 82801E C-ICH Figure 19. Ultra ATA Mode (Pausing a DMA Burst) STOP (host) DMARDY# STROBE DATA Figure 20. Ultra ATA Mode (Terminating a DMA Burst) DMARQ (drive) DMACK# (host) STOP (host) DMARDY# (drive) Strobe (host) DATA (host) Figure 21. USB Rise and Fall Times ...
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... Figure 25. SMBus Time-out SMBCLK SMBDATA Advance Information Datasheet Consecutive Transitions Paired Transitions t19 t20 t21 t135 t131 t134 t130 Start CLK ack t138 ® Intel 82801E C-ICH Crossover Points Data Crossover Level EOP Width t18 t132 Stop t137 CLK ack t138 t133 75 ...
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... Intel 82801E C-ICH Figure 26. Power Sequencing and Reset Signal Timings PWROK, VRMPWRGD Vcc3_3, Vcc1_8, V_CPU_IO V5Ref RTCRST# VccRTC Figure 27. 1.8 V/3.3 V Power Sequencing V 3.3 1.8 Voltage Figure 28 Timings CPU I/F Signals STPCLK# Break Event 76 T173 T171 T172 T170 V Time Unlatched Latched ...
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... Advance Information Datasheet < >24 N Number of PCI Clocks All Output Signals Tri-Stated ® Intel 82801E C-ICH Test Mode No Test Mode Selected XOR Chain 1 XOR Chain 2 XOR Chain 3 XOR Chain 4 All “Z” Reserved. DO NOT ATTEMPT No Test Mode Selected Test Mode Entered ...
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... Intel 82801E C-ICH 5.2 Tri-state Mode When in the tri-state mode, all outputs and bidirectional pin are tri-stated, including the XOR Chain outputs. 5.3 XOR Chain Mode In the 82801E C-ICH, provisions for Automated Test Equipment (ATE) board level testing are implemented with XOR Chains. The 82801E C-ICH signals are grouped into four independent XOR chains which are enabled individually ...
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... D15 B16 A16 C15 E14 B15 D14 A15 C14 A14 D13 C13 B13 A12 B12 D12 E12 A11 ® Intel 82801E C-ICH Pin Name Ball # Notes LDRQ0# B11 LDRQ1# C11 GPIO[21] A10 GNTA# B10 /GPIO16 REQB# /REQ5# C10 /GPIO1 GNTB# /GNT5# ...
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... Intel 82801E C-ICH Table 58. XOR Chain #2; Chain 2-1 and Chain 2-2 (RTCRST# Asserted for Five PCI Clocks while PWROK Active) Pin Name Ball # AD_18 AD_22 AD_16 STOP# PAR FRAME# AD_20 AD_15 TRDY# AD_11 AD_13 AD_4 AD_9 C/BE[0]# AD_2 AD_6 AD_3 AD_0 AD_5 AD_10 ...
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... PDIOR# PDA_0 SDD_8 SDD_9 PDA_1 SDD_7 SDD_5 SDD_10 SDD_4 PDCS3# SDD_11 SDD_2 SDD_12 SDD_3 SDD_13 SDD_1 SDD_14 SDD_0 RI# ® Intel 82801E C-ICH Ball # Notes Y14 AB15 AA15 AC16 AB16 Y15 AC17 W14 AB17 Y16 AA17 AB18 W15 AC18 W16 Y17 AA18 ...
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... Intel 82801E C-ICH Table 60. XOR Chain #4; Chain 4-1 and Chain 4-2 (RTCRST# Asserted for Seven PCI Clocks While PWROK Active) Pin Name SDIOR# SDDREQ SDIOW# SDD_15 SDA_1 SDDACK# IRQ15 SIORDY SDA_2 SDCS3# SDA_0 SDCS1# VRMPWRGD GPIO[18] GPIO[19] GPIO[20] GPIO[22] GPIO[23] A20GATE RCIN# ...
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... Advance Information Datasheet Table 61. Signals Not in XOR Chain Pin Name Ball # Notes PWROK AC9 RSMRST# W11 AB8 J23 RTCRST# M5 E13 RSM_PWROK A19 B21 F22 AB5 ® Intel 82801E C-ICH Ball # Notes W9 Y8 RTCX1 Y7 RTCX2 AA7 AA6 TP[2] AC2 T3 TP[1] AA5 OC0# AA1 RI# R5 ...
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... Intel 82801E C-ICH 5.3.1 XOR Chain Testability Algorithm Example XOR chain testing allows motherboard manufacturers to check component connectivity (e.g., opens and shorts to VCC or GND). An example algorithm to do this is shown in Table 62. Table 62. XOR Test Pattern Example Input Vector Pin ...