CY7C63723-SCT Cypress Semiconductor Corp, CY7C63723-SCT Datasheet - Page 13

• Manufacturer Part Number: CY7C63723-SCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63723-SCT

• Lead Free Status / RoHS Status: Not Compliant

Suspend Mode
The CY7C637xxC parts support a versatile low-power suspend
mode. In suspend mode, only an enabled interrupt or a LOW
state on the D–/SDATA pin will wake the part. Two options are
available. For lowest power, all internal circuits can be disabled,
so only an external event will resume operation. Alternatively, a
low-power internal wake-up timer can be used to trigger the
wake-up interrupt. This timer is described in Section , and can be
used to periodically poll the system to check for changes, such
as looking for movement in a mouse, while maintaining a low
average power.
The CY7C637xxC is placed into a low-power state by setting the
Suspend bit of the Processor Status and Control Register
(Figure
the GPIO interrupt logic, the D–/SDATA pin input receiver, and
(optionally) the wake-up timer. The clock oscillators, as well as
the free-running and Watchdog timers are shut down. Only the
occurrence of an enabled GPIO interrupt, wake-up interrupt, SPI
slave interrupt, or a LOW state on the D–/SDATA pin will wake
the part from suspend (D– LOW indicates non-idle USB activity).
Once one of these resuming conditions occurs, clocks will be
restarted and the device returns to full operation after the oscil-
lator is stable and the selected delay period expires. This delay
period is determined by selection of internal vs. external clock,
and by the state of the Ext. Clock Resume Delay as explained in
Section .
In suspend mode, any enabled and pending interrupt will wake
the part up. The state of the Interrupt Enable Sense bit (Bit 2,
Figure 33) does not have any effect. As a result, any interrupts
not intended for waking from suspend should be disabled
through the Global Interrupt Enable Register and the USB End
Point Interrupt Enable Register (Section ).
If a resuming condition exists when the suspend bit is set, the
part will still go into suspend and then awake after the appro-
priate delay time. The Run bit in the Processor Status and
Control Register must be set for the part to resume out of
suspend.
Once the clock is stable and the delay time has expired, the
microcontroller will execute the instruction following the I/O write
that placed the device into suspend mode before servicing any
interrupt requests.
To achieve the lowest possible current during suspend mode, all
I/O should be held at either V
bit interrupts (Figure 37 and Figure 38) should be disabled for
any pins that are not being used for a wake-up interrupt. This
should be done even if the main GPIO Interrupt Enable (Figure )
is off.
Typical code for entering suspend is shown below:
Document #: 38-08022 Rev. *D
...
...
...
mov a, 09h
iowr FFh
nop
...
33). All logic blocks in the device are turned off except
; All GPIO set to low-power state (no floating
;
; Select clock mode for wake-up (see Section )
; Set suspend and run bits
; Write to Status and Control Register – Enter
; This executes before any ISR
; Remaining code for exiting suspend routine
pins, and bit interrupts disabled unless using
for wake-up)
interrupts if desired for wake-up
suspend, wait for GPIO/wake-up interrupt or
USB activity
Enable
CC
GPIO
or ground. In addition, the GPIO
and/or
wake-up
timer
Clocking Mode on Wake-up from Suspend
When exiting suspend on a wake-up event, the device can be
configured to run in either Internal or External Clock mode. The
mode is selected by the state of the External Oscillator Enable
bit in the Clock Configuration Register (Figure ). Using the
Internal Clock saves the external oscillator start-up time and
keeps that oscillator off for additional power savings. The
external oscillator mode can be activated when desired, similar
to operation at power-up.
The sequence of events for these modes is as follows:
Wake in Internal Clock Mode:
Wake in External Clock Mode:
Wake-up Timer
The wake-up timer runs whenever the wake-up interrupt is
enabled, and is turned off whenever that interrupt is disabled.
Operation is independent of whether the device is in suspend
mode or if the global interrupt bit is enabled. Only the Wake-up
Timer Interrupt Enable bit (Figure ) controls the wake-up timer.
Once this timer is activated, it will give interrupts after its time-out
period (see below). These interrupts continue periodically until
the interrupt is disabled. Whenever the interrupt is disabled, the
wake-up timer is reset, so that a subsequent enable always
results in a full wake-up time.
The wake-up timer can be adjusted by the user through the
Wake-up Timer Adjust bits in the Clock Configuration Register
(Figure ). These bits clear on reset. In addition to allowing the
user to select a range for the wake-up time, a firmware algorithm
can be used to tune out initial process and operating condition
variations in this wake-up time. This can be done by timing the
wake-up interrupt time with the accurate 1.024-ms timer
interrupt, and adjusting the Timer Adjust bits accordingly to
approximate the desired wake-up time.
1. Before entering suspend, clear bit 0 of the Clock Configuration
2. Enter suspend mode by setting the suspend bit of the
3. After a wake-up event, the internal clock starts immediately
4. A time-out period of 8 μs passes, and then firmware execution
5. At some later point, to activate External Clock mode, set bit 0
1. Before entering suspend, the external clock must be selected
2. Enter suspend mode by setting the suspend bit of the
3. After a wake-up event, the external oscillator is started. The
4. After an additional time-out period (128 μs or 4 ms, see
Register. This selects Internal clock mode after suspend.
Processor Status and Control Register.
(within 2 μs).
begins.
of the Clock Configuration Register. This halts the internal
clocks while the external clock becomes stable. After an
additional time-out (128 μs or 4 ms, see Section ), firmware
execution resumes.
by setting bit 0 of the Clock Configuration Register. Make sure
this bit is still set when suspend mode is entered. This selects
External clock mode after suspend.
Processor Status and Control Register.
clock is monitored for stability (this takes approximately
50–100 μs with a ceramic resonator).
Section ), firmware execution resumes.
CY7C63722C
CY7C63723C
CY7C63743C
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