CY7C63723-SCT Cypress Semiconductor Corp, CY7C63723-SCT Datasheet - Page 4

• Manufacturer Part Number: CY7C63723-SCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63723-SCT

• Lead Free Status / RoHS Status: Not Compliant

Programming Model
Refer to the CYASM Assembler User’s Guide for more details on
firmware operation with the CY7C637xxC microcontrollers.
Program Counter (PC)
The 14-bit program counter (PC) allows access for up to 8
Kbytes of EPROM using the CY7C637xxC architecture. The
program counter is cleared during reset, such that the first
instruction executed after a reset is at address 0x0000. This
instruction is typically a jump instruction to a reset handler that
initializes the application.
The lower 8 bits of the program counter are incremented as
instructions are loaded and executed. The upper six bits of the
program counter are incremented by executing an XPAGE
instruction. As a result, the last instruction executed within a
256-byte “page” of sequential code should be an XPAGE
instruction. The assembler directive “XPAGEON” will cause the
assembler to insert XPAGE instructions automatically. As
instructions can be either one or two bytes long, the assembler
may occasionally need to insert a NOP followed by an XPAGE
for correct execution.
The program counter of the next instruction to be executed, carry
flag, and zero flag are saved as two bytes on the program stack
during an interrupt acknowledge or a CALL instruction. The
program counter, carry flag, and zero flag are restored from the
program stack only during a RETI instruction.
Please note the program counter cannot be accessed directly by
the firmware. The program stack can be examined by reading
SRAM from location 0x00 and up.
8-bit Accumulator (A)
The accumulator is the general-purpose, do everything register
in the architecture where results are usually calculated.
8-bit Index Register (X)
The index register “X” is available to the firmware as an auxiliary
accumulator. The X register also allows the processor to perform
indexed operations by loading an index value into X.
8-bit Program Stack Pointer (PSP)
During a reset, the program stack pointer (PSP) is set to zero.
This means the program “stack” starts at RAM address 0x00 and
“grows” upward from there. Note that the program stack pointer
is directly addressable under firmware control, using the MOV
PSP,A instruction. The PSP supports interrupt service under
hardware control and CALL, RET, and RETI instructions under
firmware control.
During an interrupt acknowledge, interrupts are disabled and the
program counter, carry flag, and zero flag are written as two
bytes of data memory. The first byte is stored in the memory
addressed by the program stack pointer, then the PSP is incre-
mented. The second byte is stored in memory addressed by the
program stack pointer and the PSP is incremented again. The
net effect is to store the program counter and flags on the
program “stack” and increment the program stack pointer by two.
The return from interrupt (RETI) instruction decrements the
program stack pointer, then restores the second byte from
memory addressed by the PSP. The program stack pointer is
Document #: 38-08022 Rev. *D
decremented again and the first byte is restored from memory
addressed by the PSP. After the program counter and flags have
been restored from stack, the interrupts are enabled. The effect
is to restore the program counter and flags from the program
stack, decrement the program stack pointer by two, and reenable
interrupts.
The call subroutine (CALL) instruction stores the program
counter and flags on the program stack and increments the PSP
by two.
The return from subroutine (RET) instruction restores the
program counter, but not the flags, from program stack and
decrements the PSP by two.
Note that there are restrictions in using the JMP, CALL, and
INDEX instructions across the 4-KByte boundary of the program
memory. Refer to the CYASM Assembler User’s Guide for a
detailed description.
8-bit Data Stack Pointer (DSP)
The data stack pointer (DSP) supports PUSH and POP instruc-
tions that use the data stack for temporary storage. A PUSH
instruction will pre-decrement the DSP, then write data to the
memory location addressed by the DSP. A POP instruction will
read data from the memory location addressed by the DSP, then
post-increment the DSP.
During a reset, the Data Stack Pointer will be set to zero. A PUSH
instruction when DSP equals zero will write data at the top of the
data RAM (address 0xFF). This would write data to the memory
area reserved for a FIFO for USB endpoint 0. In non-USB appli-
cations, this works fine and is not a problem.
For USB applications, the firmware should set the DSP to an
appropriate location to avoid a memory conflict with RAM
dedicated to USB FIFOs. The memory requirements for the USB
endpoints are shown in Section . For example, assembly instruc-
tions to set the DSP to 20h (giving 32 bytes for program and data
stack combined) are shown below.
Address Modes
The CY7C637xxC microcontrollers support three addressing
modes for instructions that require data operands: data, direct,
and indexed.
Data
The “Data” address mode refers to a data operand that is actually
a constant encoded in the instruction. As an example, consider
the instruction that loads A with the constant 0x30:
■
This instruction will require two bytes of code where the first byte
identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction will be the
constant “0xE8h”. A constant may be referred to by name if a
prior “EQU” statement assigns the constant value to the name.
For example, the following code is equivalent to the example
shown above.
■
MOV A, 30h
DSPINIT: EQU 30h
MOV A,20h
or less to avoid USB FIFOs)
SWAP A,DSP ; swap accumulator value into DSP register
; Move 20 hex into Accumulator (must be D8h
CY7C63722C
CY7C63723C
CY7C63743C
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