CY7C63723-SCT Cypress Semiconductor Corp, CY7C63723-SCT Datasheet - Page 17

• Manufacturer Part Number: CY7C63723-SCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63723-SCT

• Lead Free Status / RoHS Status: Not Compliant

USB Enumeration
A typical USB enumeration sequence is shown below. In this
description, ‘Firmware’ refers to embedded firmware in the
CY7C637xxC controller.
USB Port Status and Control
USB status and control is regulated by the USB Status and
Control Register as shown in
Figure 14. USB Status and Control Register (Address 0x1F)
Bit 7: PS/2 Pull-up Enable
Document #: 38-08022 Rev. *D
Name
Read/
Reset
1. The host computer sends a SETUP packet followed by a
2. Firmware decodes the request and retrieves its Device
3. The host computer performs a control read sequence and
4. After receiving the descriptor, the host sends a SETUP packet
5. Firmware stores the new address in its USB Device Address
6. The host sends a request for the Device descriptor using the
7. Firmware decodes the request and retrieves the Device
8. The host performs a control read sequence and Firmware
9. The host generates control reads from the device to request
10.Once the device receives a Set Configuration request, its
11.Firmware should take appropriate action for Endpoint 1
Write
Bit #
Bit
DATA packet to USB address 0 requesting the Device de-
scriptor.
descriptor from the program memory tables.
Firmware responds by sending the Device descriptor over the
USB bus, via the on-chip FIFO.
followed by a DATA packet to address 0 assigning a new USB
address to the device.
Register after the no-data control sequence completes.
new USB address.
descriptor from program memory tables.
responds by sending its Device descriptor over the USB bus.
the Configuration and Report descriptors.
functions may now be used.
and/or 2 transactions, which may occur from this point.
This bit is used to enable the internal PS/2 pull-up resistors
on the SDATA and SCLK pins. Normally the output high level
on these pins is V
Pull-up
Enable
PS/2
R/W
7
0
Enable
VREG
R/W
6
0
CC
Interrupt
, but note that the output will be clamped
Activity
Reset-
Mode
PS/2
USB
R/W
5
0
Figure
Reserved USB
14.
4
0
-
Activity
R/W
Bus
3
0
0 0 0
Forcing
D+/D–
R/W
2:0
Bit
Bit 6: V
Bit 5: USB-PS/2 Interrupt Select
Bit 4: Reserved. Must be written as a ‘0’.
Bit 3: USB Bus Activity
Bit [2:0]: D+/D– Forcing Bit [2:0]
to approximately 1 Volt above V
set, or if the Device Address is enabled (bit 7 of the USB
Device Address Register, Figure 15).
1 = Enable PS/2 Pull-up resistors. The SDATA and SCLK pins
are pulled up internally to V
mately 5 kΩ (see Section for the value of R
0 = Disable PS/2 Pull-up resistors.
A 3.3V voltage regulator is integrated on chip to provide a
voltage source for a 1.5-kΩ pull-up resistor connected to the
D– pin as required by the USB Specification. Note that the
VREG output has an internal series resistance of approxi-
mately 200Ω, the external pull-up resistor required is approx-
imately 1.3-kΩ (see Figure 19).
1 = Enable the 3.3V output voltage on the VREG pin.
0 = Disable. The VREG pin can be configured as an input.
This bit allows the user to select whether an USB bus reset
interrupt or a PS/2 activity interrupt will be generated when
the interrupt conditions are detected.
1 = PS/2 interrupt mode. A PS/2 activity interrupt will occur if
the SDATA pin is continuously LOW for 128 to 256 μs.
0 = USB interrupt mode (default state). In this mode, a USB
bus reset interrupt will occur if the single ended zero (SE0, D–
and D+ are LOW) exists for 128 to 256 μs.
See Section for more details.
The Bus Activity bit is a “sticky” bit that detects any non-idle
USB event has occurred on the USB bus. Once set to HIGH
by the SIE to indicate the bus activity, this bit retains its logical
HIGH value until firmware clears it. Writing a ‘0’ to this bit
clears it; writing a ‘1’ preserves its value. The user firmware
should check and clear this bit periodically to detect any loss
of bus activity. Firmware can clear the Bus Activity bit, but only
the SIE can set it. The 1.024-ms timer interrupt service routine
is normally used to check and clear the Bus Activity bit.
1 = There has been bus activity since the last time this bit was
cleared. This bit is set by the SIE.
0 = No bus activity since last time this bit was cleared (by
firmware).
Forcing bits allow firmware to directly drive the D+ and D–
pins, as shown in Table 4. Outputs are driven with controlled
edge rates in these modes for low EMI. For forcing the D+ and
D– pins in USB mode, D+/D– Forcing Bit 2 should be 0. Set-
ting D+/D– Forcing Bit 2 to ‘1’ puts both pins in an open-drain
mode, preferred for applications such as PS/2 or LED driving.
REG
Enable
CC
with two resistors of approxi-
REG
if the VREG Enable bit is
CY7C63722C
CY7C63723C
CY7C63743C
PS2
Page 17 of 53
).
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