CY7C63723-SCT Cypress Semiconductor Corp, CY7C63723-SCT Datasheet - Page 27

• Manufacturer Part Number: CY7C63723-SCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63723-SCT

• Lead Free Status / RoHS Status: Not Compliant

The four Capture Timer Data Registers are read-only, and are
shown in Figure through Figure 30.
Out of the 12-bit free running timer, the 8-bit captured in the
Capture Timer Data Registers are determined by the Prescale
Bit [2:0] in the Capture Timer Configuration Register (Figure 32).
Capture Timer A-Rising, Data Register (Address 0x40.)
Figure 28. Capture Timer A-Falling, Data Register
(Address 0x41)
Figure 29. Capture Timer B-Rising, Data Register
(Address 0x42)
Figure 30. Capture Timer B-Falling, Data Register
(Address 0x43)
Document #: 38-08022 Rev. *D
Read/Write
Read/Write
Read/Write
Bit Name
Bit Name
Read/Write
Bit Name
Bit Name
Reset
Reset
Bit #
Bit #
Reset
Reset
Bit #
Bit #
R
R
7
0
7
0
R
R
7
0
7
0
R
R
6
0
6
0
R
R
6
0
6
0
Capture B Falling Data
Capture B Rising Data
Capture A Falling Data
Capture A Rising Data
R
R
5
0
5
0
R
R
5
0
5
0
R
R
4
0
4
0
R
R
4
0
4
0
R
R
3
0
3
0
R
R
3
0
3
0
R
R
2
0
2
0
R
R
2
0
2
0
R
1
0
R
1
0
R
R
1
0
1
0
R
R
0
0
0
0
R
0
0
R
0
0
Figure 31. Capture Timer Status Register (Address 0x45)
Bit [7:4]: Reserved.
Bit [3:0]: Capture A/B, Falling/Rising Event
Figure 32. Capture Timer Configuration Register
(Address 0x44)
Name
Read/
Reset
Write
Name
Read/
Reset 0
Bit #
Write
Bit #
Bit
Bit
These bits record the occurrence of any rising or falling edges
on the capture GPIO pins. Bits in this register are cleared by
reading the corresponding data register.
1 = A rising or falling event that matches the pin’s rising/falling
condition has occurred.
0 = No event that matches the pin’s rising or falling edge con-
dition.
Because both Capture A events (rising and falling) share an
interrupt, user’s firmware needs to check the status of both
Capture A Falling and Rising Event bits to determine what
caused the interrupt. This is also true for Capture B events.
Edge
Hold
First
R/W R/W R/W R/W
7
-
7
0
Reserved
6
0
-
Prescale Bit
6
0
5
0
-
[2:0]
5
0
4
0
-
Capture
Falling
Event
4
0
B
R
3
0
Capture
Enable
Falling
R/W
Int
B
3
0
Capture
Rising
Event
R
2
B
0
Capture
Enable
Rising
R/W
Int
B
2
0
CY7C63722C
CY7C63723C
CY7C63743C
Capture
Falling
Event
Capture
A
R
1
0
Enable
Falling
R/W
Int
Page 27 of 53
1
A
0
Capture
Rising
Event
Capture
Enable
R
Rising
0
A
0
R/W
Int
0
A
0
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