CY7C63723-SCT Cypress Semiconductor Corp, CY7C63723-SCT Datasheet - Page 26

• Manufacturer Part Number: CY7C63723-SCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63723-SCT

• Lead Free Status / RoHS Status: Not Compliant

Timer Capture Registers
Four 8-bit capture timer registers provide both rising- and falling-edge event timing capture on two pins. Capture Timer A is connected
to Pin 0.0, and Capture Timer B is connected to Pin 0.1. These can be used to mark the time at which a rising or falling event occurs
at the two GPIO pins. Each timer will capture eight bits of the free-running timer into its Capture Timer Data Register if a rising or
falling edge event that matches the specified rising or falling edge condition at the pin. A prescaler allows selection of the capture
timer tick size. Interrupts can be individually enabled for the four capture registers. A block diagram is shown in
Document #: 38-08022 Rev. *D
Capture A Rising Int Enable
Bit 0, Reg 0x44
Capture A Falling Int Enable
Bit 1, Reg 0x44
Capture B Rising Int Enable
Bit 2, Reg 0x44
Capture B Falling Int Enable
Bit 3, Reg 0x44
GPIO
P0.0
GPIO
P0.1
First Edge Hold
Bit 7, Reg 0x44
Rising
Edge
Detect
Falling
Edge
Detect
Rising
Edge
Detect
Falling
Edge
Detect
Free-running Timer
11
10
Figure 27. Capture Timers Block Diagram
9
Prescaler
8
Mux
7
6
5
Timer A Rising Edge Time
Timer A Falling Edge Time
Timer B Rising Edge Time
Timer B Falling Edge Time
8-bit Capture Registers
4
3
2
Capture Timer A Interrupt Request
Capture Timer B Interrupt Request
1
0
1 MHz
Clock
CY7C63722C
CY7C63723C
CY7C63743C
Figure
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