ISP1183BS STEricsson, ISP1183BS Datasheet - Page 19

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1183_3
Product data sheet
10.3 DACK-only mode
10. The 8237 de-asserts the DACK_N output, indicating that the ISP1183 must stop
11. The 8237 places bus control signals (MEMR_N, MEMW_N, IOR_N and IOW_N) and
12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating bus
For a typical bulk transfer, the preceding process is repeated 64 times, once for each byte.
After each byte, the Address register in the DMA controller is incremented and the byte
counter is decremented.
DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware Configuration
register (see
example of the ISP1183 in DACK-only DMA mode is given in
Table 9.
In DACK-only mode, the ISP1183 uses the DACK signal as data strobe. Input signals
RD_N and WR_N are ignored. This mode is used in CPU systems that have a single
address space for memory and I/O access. Such systems have no separate MEMW_N
and MEMR_N signals: the RD_N and WR_N signals are also used as memory data
strobes.
Symbol
DREQ
DACK
RD_N
WR_N
7. The ISP1183 places the byte or word to be transferred on data bus lines because its
8. The 8237 waits one DMA clock period and then de-asserts MEMW_N and IOR_N.
9. The ISP1183 de-asserts the DREQ signal to indicate to the 8237 that DMA is no
RD_N signal was asserted by the 8237.
This latches and stores the byte or word at the desired memory location. It also
informs the ISP1183 that data on bus lines has been transferred.
longer needed. In single-cycle mode, this is done after each byte or word; in burst
mode following the last transferred byte or word of the DMA cycle.
placing data on the bus.
address lines in 3-state and de-asserts the HRQ signal, informing the CPU that it has
released the bus.
control lines (MEMR_N, MEMW_N, IOR_N and IOW_N) and address lines, the CPU
resumes the execution of instructions.
DACK-only mode: pin functions
Description
DMA request
DMA acknowledge
read strobe
write strobe
Table
20). The pin functions for this mode are shown in
Rev. 03 — 20 January 2009
I/O
O
I
I
I
Low-power USB Peripheral Controller with DMA
Function
ISP1183 requests a DMA transfer
as data strobe
not used
not used
DMA controller confirms the transfer; also functions
Figure
© ST-NXP Wireless 2009. All rights reserved.
10.
Table
ISP1183
9. A typical
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