ISP1183BS STEricsson, ISP1183BS Datasheet - Page 29

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 18.
[1]
ISP1183_3
Product data sheet
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
Mode register: bit allocation
12.1.3 Mode register (R/W: B9h/B8h)
12.1.4 Hardware Configuration register (R/W: BBh/BAh)
reserved
R/W
0
7
[1]
This command accesses the ISP1183 Mode register, which consists of 1 byte (bit
allocation: see
The Mode register controls the DMA bus width, resume and suspend modes, interrupt
activity and SoftConnect operation. It can be used to enable debug mode, in which all
errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code: B8h/B9h — write or read Mode register
Transaction — write or read 1 byte
Table 19.
This command accesses the Hardware Configuration register that consists of 2 bytes.
The first (lower) byte contains the device configuration and control values, the second
(upper) byte holds clock control bits and the clock division factor. The bit allocation is
given in
The Hardware Configuration register controls the connection to the USB bus, clock
activity and power supply during the suspend state, output clock frequency, DMA
operating mode and pin configurations (polarity, signaling mode).
Code: BAh/BBh — write or read Hardware Configuration register
Transaction — write or read 2 bytes
Bit
7
6
5
4
3
2
1
0
reserved
R/W
6
0
Table
Mode register: bit description
Symbol
reserved
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
20. A bus reset will not change any of the programmed bit values.
Table
GOSUSP
R/W
5
0
18). In 16-bit bus mode, the upper byte is ignored.
Rev. 03 — 20 January 2009
Description
This bit should be always written as logic 0.
reserved
Writing logic 1, followed by logic 0 will activate suspend mode.
reserved
Logic 1 enables all interrupts. Bus reset value: unchanged.
Logic 1 enables debug mode, in which all NAKs and errors will
generate an interrupt. Logic 0 selects normal operation, in which
interrupts are generated on every ACK (bulk endpoints) or after every
data transfer (isochronous endpoints). Bus reset value: unchanged.
reserved
Logic 1 enables SoftConnect (see
EXTPUL = 1 in the Hardware Configuration register (see
Bus reset value: unchanged.
reserved
R/W
4
0
Low-power USB Peripheral Controller with DMA
INTENA
R/W
0
3
[1]
DBGMOD
R/W
0
2
Section
[1]
7.4). This bit is ignored if
reserved
© ST-NXP Wireless 2009. All rights reserved.
R/W
0
1
[1]
ISP1183
Table
SOFTCT
R/W
0
0
[1]
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20).