ISP1183BS STEricsson, ISP1183BS Datasheet - Page 27

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 13.
[1]
[2]
[3]
ISP1183_3
Product data sheet
Name
DMA commands
Write or read DMA Function
and Scratch register
Write or read DMA
Configuration
Write or read DMA Counter
General commands
Read Control OUT Error Code Error Code register
Read Control IN Error Code
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
Read Frame Number
Read Chip ID
Read Interrupt register
Validating an OUT endpoint buffer causes unpredictable behavior of the ISP1183.
Clearing an IN endpoint buffer causes unpredictable behavior of the ISP1183.
Reads a copy of the Status register: executing this command does not clear any status bits or interrupt bits.
Command and register overview
12.1.1 Endpoint Configuration register (R/W: 30h to 3Fh/20h to 2Fh)
12.1 Initialization commands
Initialization commands are used during the enumeration process of the USB network.
These commands are used to configure and enable embedded endpoints. They also set
the USB assigned address of the ISP1183 and perform device reset.
This command accesses the Endpoint Configuration Register (ECR) of the target
endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction (OUT/IN),
FIFO size and buffering scheme. It also enables the endpoint FIFO. The register bit
allocation is shown in
The allocation of FIFO memory takes place only after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although control endpoints
have fixed configurations, they must be included in the initialization sequence and
configured with their default values (see
endpoint 14 is configured.
Remark: If any change is made to an endpoint configuration that affects the allocated
memory (size, enable/disable), the FIFO memory contents of all endpoints become
invalid. Therefore, all valid data must be removed from enabled endpoints before
changing the configuration.
Code: 20h to 2Fh — write (control OUT, control IN, endpoints 1 to 14)
Destination
DMA Function and Scratch
register
DMA Configuration
register
DMA Counter register
endpoint 0 OUT
Error Code register
endpoint 0 IN
Error Code register
endpoints 1 to 14
all registers with write
access
Interrupt register
Frame Number register
Chip ID register
…continued
Rev. 03 — 20 January 2009
Table
14. A bus reset will disable all endpoints.
Code
B2h/B3h
F0h/F1h
F2h/F3h
A0h
A1h
A2h to AFh read 1 byte
B0h
B4h
B5h
C0h
Low-power USB Peripheral Controller with DMA
Table
Transaction
write or read
2 bytes
write or read
2 bytes
write or read
2 bytes
read 1 byte
read 1 byte
write 2 bytes
read 1 byte or
2 bytes
read 2 bytes
read 4 bytes
4). Automatic FIFO allocation starts when
Reference
Section 12.3.1 on page 35
Section 12.3.2 on page 36
Section 12.3.3 on page 36
Section 12.4.1 on page 37
Section 12.4.2 on page 38
Section 12.4.3 on page 39
Section 12.4.4 on page 39
Section 12.4.5 on page 40
© ST-NXP Wireless 2009. All rights reserved.
ISP1183
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