ISP1181BBSUM STEricsson, ISP1181BBSUM Datasheet - Page 10

• Manufacturer Part Number: ISP1181BBSUM
• Manufacturer: STEricsson

Specifications of ISP1181BBSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

CD00222684
Product data sheet
7.5 GoodLink
7.6 Bit clock recovery
7.7 Voltage regulator
7.8 PLL clock multiplier
7.9 Parallel I/O (PIO) and Direct Memory Access (DMA) interface
V
V
sensing, (D+, D-) is decoupled when no V
on the (D+, D-) lines, it is not taken into account. This ensures that the peripheral remains
in the suspend state.
Remark: Note that the tolerance of the internal resistors is 25 %. This is higher than the
5 % tolerance specified by the USB specification. However, the overall voltage
specification for the connection can still be met with a good margin. The decision to make
use of this feature lies with the USB equipment designer.
Indication of a good USB connection is provided at pin GL through GoodLink technology.
During enumeration, the LED indicator will blink on momentarily. When the ISP1181B has
been successfully enumerated (the peripheral address is set), the LED indicator will
remain permanently on. Upon each successful packet transfer (with ACK) to and from the
ISP1181B, the LED will blink off for 100 ms. During ‘suspend’ state, the LED will remain
off.
This feature provides a user-friendly indication of the status of the USB peripheral, the
connected hub, and the USB traffic. It is a useful field diagnostics tool for isolating faulty
equipment. It can therefore help to reduce field support and hotline overhead.
The bit clock recovery circuit recovers the clock from the incoming USB data stream using
a 4 times over-sampling principle. It is able to track jitter and frequency drift as specified
by the USB Specification Rev. 2.0.
A 5 V-to-3.3 V voltage regulator is integrated on-chip to supply the analog transceiver and
internal logic. This voltage is available at pin V
resistor on the D+ line. Alternatively, the ISP1181B provides SoftConnect technology via
an integrated 1.5 kΩ pull-up resistor (see
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This
allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external
components are required for the operation of the PLL.
A generic PIO interface is defined for speed and ease-of-use. It also allows direct
interfacing to most microcontrollers. To a microcontroller, the ISP1181B appears as a
memory device with an 8/16-bit data bus and a 1-bit address line. The ISP1181B supports
both multiplexed and non-multiplexed address and data buses.
The ISP1181B can also be configured as a DMA slave device to allow more efficient data
transfer. One of the 14 endpoint FIFOs may directly transfer data to/from the local shared
memory. The DMA interface can be configured independently from the PIO interface.
BUS
BUS
sensing prevents the peripheral from wake-up when V
sensing, any activity or noise on (D+, D-) might wake up the peripheral. With V
Rev. 05 — 25 August 2010
Section
BUS
is present. Therefore, even if there is noise
reg(3.3)
7.4).
Full-speed USB peripheral controller
to supply an external 1.5 kΩ pull-up
BUS
is not present. Without
© ST-ERICSSON 2010. All rights reserved.
ISP1181B
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BUS