ISP1181BBSUM STEricsson, ISP1181BBSUM Datasheet - Page 40

• Manufacturer Part Number: ISP1181BBSUM
• Manufacturer: STEricsson

Specifications of ISP1181BBSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

Table 48.
13. Interrupts
CD00222684
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Interrupt Register: bit allocation
BUSTATUS
EP14
EP6
31
23
15
R
R
R
R
0
0
0
7
0
Table 49.
Figure 8
logged in a status bit of the Interrupt Register. Corresponding bits in the Interrupt Enable
Register determine whether or not an event will generate an interrupt.
Interrupts can be masked globally by means of the INTENA bit of the Mode Register (see
Table
Bit
31 to 24
23 to 10
9
8
7
6
5
4
3
2
1
0
SP_EOT
EP13
19).
EP5
30
22
14
R
R
R
R
0
0
0
6
0
shows the interrupt logic of the ISP1181B. Each of the indicated USB events is
Interrupt Register: bit description
Symbol
-
EP14 to EP1
EP0IN
EP0OUT
BUSTATUS
SP_EOT
PSOF
SOF
EOT
SUSPND
RESUME
RESET
PSOF
EP12
EP4
29
21
13
R
R
R
R
0
0
0
5
0
Rev. 05 — 25 August 2010
Description
reserved
A logic 1 indicates the interrupt source(s): endpoint 14 to 1.
A logic 1 indicates the interrupt source: control IN endpoint.
A logic 1 indicates the interrupt source: control OUT endpoint.
It monitors the current USB bus status (0 = awake, 1 = suspend).
A logic 1 indicates that an EOT interrupt has occurred for a short
packet.
A logic 1 indicates that an interrupt is issued every 1 ms because of
the Pseudo SOF; after 3 missed SOFs ‘suspend’ state is entered.
A logic 1 indicates that a SOF condition was detected.
A logic 1 indicates that an internal EOT condition was generated by
the DMA Counter reaching zero.
A logic 1 indicates that an ‘awake’ to ‘suspend’ change of state was
detected on the USB bus.
A logic 1 indicates that a ‘resume’ state was detected.
A logic 1 indicates that a bus reset condition was detected.
EP11
SOF
EP3
28
20
12
R
R
R
R
0
0
0
4
0
reserved
EP10
EOT
EP2
27
19
11
R
R
R
R
0
0
0
3
0
Full-speed USB peripheral controller
SUSPND
EP9
EP1
26
18
10
R
R
R
R
0
0
0
2
0
RESUME
EP0IN
© ST-ERICSSON 2010. All rights reserved.
EP8
ISP1181B
25
17
R
R
R
R
0
0
9
0
1
0
EP0OUT
RESET
EP7
24
16
R
R
R
R
0
0
8
0
0
0
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