ISP1181BBSUM STEricsson, ISP1181BBSUM Datasheet - Page 66

• Manufacturer Part Number: ISP1181BBSUM
• Manufacturer: STEricsson

Specifications of ISP1181BBSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

26. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. ISP1181B with a 3.0 V to 3.6 V supply. . . . . . . . .42
Fig 11. Typical oscillator circuit. . . . . . . . . . . . . . . . . . . .42
Fig 12. Oscillator and LazyClock logic. . . . . . . . . . . . . . .43
Fig 13. CLKOUT signal timing at ‘suspend’ and
Fig 14. Power-on reset timing. . . . . . . . . . . . . . . . . . . . .44
Fig 15. Source differential data-to-EOP transition skew and
Fig 16. Receiver differential data jitter. . . . . . . . . . . . . . .49
Fig 17. Receiver SE0 width tolerance. . . . . . . . . . . . . . .49
Fig 18. Parallel interface read timing (I/O and 8237
Fig 19. Parallel interface write timing (I/O and 8237
Fig 20. ALE timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Fig 21. Write command + write data cycle timing. . . . . .52
Fig 22. Write data + write command cycle timing. . . . . .53
Fig 23. Write command + read data cycle timing. . . . . . .53
Fig 24. Read data + write command cycle timing. . . . . .53
Fig 25. DMA timing in 8237 compatible mode. . . . . . . . .54
Fig 26. DMA read timing in DACK-only mode.. . . . . . . . .55
Fig 27. DMA write timing in DACK-only mode. . . . . . . . .55
Fig 28. EOT timing in single-cycle DMA mode. . . . . . . .55
Fig 29. Burst mode DMA timing. . . . . . . . . . . . . . . . . . . .56
Fig 30. EOT timing in burst mode DMA. . . . . . . . . . . . . .57
Fig 31. Typical interface circuit for bus configuration mode 0
Fig 32. Typical interface circuit for bus configuration mode 2
Fig 33. Load impedance for D+ and D- pins. . . . . . . . . .61
Fig 34. TSSOP48 package outline. . . . . . . . . . . . . . . . . .62
Fig 35. HVQFN48 package outline. . . . . . . . . . . . . . . . . .63
CD00222684
Product data sheet
SUSPEND and WAKEUP signals in a powered-off
modem application. . . . . . . . . . . . . . . . . . . . . . . .22
‘resume’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
EOP width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
compatible DMA). . . . . . . . . . . . . . . . . . . . . . . . .51
compatible DMA). . . . . . . . . . . . . . . . . . . . . . . . .51
(shared ports: 16-bit PIO, 16-bit DMA). . . . . . . .58
(shared ports: 8-bit PIO, 8-bit DMA). . . . . . . . . .59
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin configuration TSSOP48. . . . . . . . . . . . . . . . . .4
Pin configuration HVQFN48. . . . . . . . . . . . . . . . .5
ISP1181B in 8237 compatible DMA mode. . . . . .16
ISP1181B in DACK-only DMA mode. . . . . . . . . .18
Suspend and resume timing. . . . . . . . . . . . . . . . .21
Interrupt logic. . . . . . . . . . . . . . . . . . . . . . . . . . . .41
ISP1181B with a 4.0 V to 5.5 V supply. . . . . . . . .42
Rev. 05 — 25 August 2010
Full-speed USB peripheral controller
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ISP1181B
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