ISP1181BBSUM STEricsson, ISP1181BBSUM Datasheet - Page 27

• Manufacturer Part Number: ISP1181BBSUM
• Manufacturer: STEricsson

Specifications of ISP1181BBSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

Table 18.
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CD00222684
Product data sheet
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
Mode Register: bit allocation
12.1.3 Write/Read Mode Register
12.1.4 Write/Read Hardware Configuration
DMAWD
R/W
0
7
[1]
This command is used to access the ISP1181B Mode Register, which consists of 1 byte
(bit allocation: see
The Mode Register controls the DMA bus width, resume and suspend modes, interrupt
activity and SoftConnect operation. It can be used to enable debug mode, where all errors
and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 — write/read Mode Register
Transaction — write/read 1 byte
Table 19.
This command is used to access the Hardware Configuration Register, which consists of
2 bytes. The first (lower) byte contains the device configuration and control values, the
second (upper) byte holds the clock control bits and the clock division factor. The bit
allocation is given in
values.
The Hardware Configuration Register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA operating
mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read Hardware Configuration Register
Bit
7
6
5
4
3
2
1
0
reserved
R/W
6
0
Mode Register: bit description
Symbol
DMAWD
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
GOSUSP
Table
R/W
5
0
Table
Rev. 05 — 25 August 2010
18). In 16-bit bus mode the upper byte is ignored.
20. A bus reset will not change any of the programmed bit
Description
A logic 1 selects 16-bit DMA bus width (bus configuration modes
0 and 2). A logic 0 selects 8-bit DMA bus width.
Bus reset value: unchanged.
reserved
Writing a logic 1 followed by a logic 0 will activate ‘suspend’ mode.
reserved
A logic 1 enables all interrupts. Bus reset value: unchanged.
A logic 1 enables debug mode. where all NAKs and errors will
generate an interrupt. A logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints).
Bus reset value: unchanged.
reserved
A logic 1 enables SoftConnect (see
if EXTPUL = 1 in the Hardware Configuration Register (see
Table
reserved
R/W
4
0
20). Bus reset value: unchanged.
INTENA
R/W
0
3
[1]
Full-speed USB peripheral controller
DBGMOD
R/W
0
2
[1]
Section
reserved
7.4). This bit is ignored
© ST-ERICSSON 2010. All rights reserved.
R/W
ISP1181B
0
1
[1]
SOFTCT
R/W
0
0
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