PSD834F2-15M STMicroelectronics, PSD834F2-15M Datasheet - Page 50

• Manufacturer Part Number: PSD834F2-15M
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-15M

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD834F2V
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 6. The addresses in Table 6 are the
offsets in hexadecimal from the base of the CSIOP
register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 21, are used for setting the
Port configurations. The default Power-up state for
each register in Table 21 is 00h.
Control Register. Any bit reset to '0' in the Con-
trol Register sets the corresponding port pin to
MCU I/O Mode, and a 1 sets it to Address Out
Mode. The default mode is MCU I/O. Only Ports A
and B have an associated Control Register.
Direction Register. The Direction Register, in
conjunction with the output enable (except for Port
D), controls the direction of data flow in the I/O
Ports. Any bit set to '1' in the Direction Register
causes the corresponding pin to be an output, and
any bit set to '0' causes it to be an input. The de-
fault mode for all port pins is input.
Figure 24 and Figure 25 show the Port Architec-
ture diagrams for Ports A/B and C, respectively.
The direction of data flow for Ports A, B, and C are
controlled not only by the direction register, but
also by the output enable product term from the
PLD AND Array. If the output enable product term
is not active, the Direction Register has sole con-
trol of a given pin’s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 24. Since
Port D only contains three pins (shown in Figure
27), the Direction Register for Port D has only the
three least significant bits active.
Drive Select Register. The Drive Select Register
configures the pin driver as Open Drain or CMOS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
50/95
Note that the slew rate is a measurement of the
rise and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to '1.' The default rate is slow slew.
Table 25 shows the Drive Register for Ports A, B,
C, and D. It summarizes which pins can be config-
ured as Open Drain outputs and which pins the
slew rate can be set for.
Table 21. Port Configuration Registers (PCR)
Note: 1. See Table 25 for Drive Register bit definition.
Table 22. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 23. Port Pin Direction Control, Output
Enable P.T. Defined
Table 24. Port Direction Assignment Example
Control
Direction
Drive Select
0
1
0
0
1
1
0
Bit 7
Register Name
Direction Register Bit
Register Bit
Direction
0
Bit 6
1
0
Bit 5
A,B
A,B,C,D
A,B,C,D
0
1
0
1
Output Enable
0
Bit 4
Port
P.T.
Input
Output
0
Bit 3
Port Pin Mode
1
Bit 2
WRITE/READ
WRITE/READ
WRITE/READ
Input
Output
Output
Output
Port Pin Mode
MCU Access
1
Bit 1
1
Bit 0