PSD834F2-15M STMicroelectronics, PSD834F2-15M Datasheet - Page 61

• Manufacturer Part Number: PSD834F2-15M
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-15M

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

RESET TIMING AND DEVICE STATUS AT RESET
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration t
steady. During this period, the device loads inter-
nal configurations, clears some of the registers
and sets the Flash memory into Operating mode.
After the rising edge of Reset (RESET), the PSD
remains in the Reset mode for an additional peri-
od, t
lowed.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR, CNTL0) High, during Power On Re-
set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
Flash memory WRITE cycle initiation is prevented
automatically when V
Warm Reset
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
Figure 30. Reset (RESET) Timing
V
RESET
OPR
CC
, before the first memory access is al-
CC
Power-On Reset
V
t NLNH-PO
CC
is below V
(min)
NLNH-PO
LKO
after V
.
t OPR
CC
is
t
device is operational after warm reset. Figure 30
shows the timing of the Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 32 shows the I/O pin, register and PLD sta-
tus during Power On Reset, warm reset and Pow-
er-down mode. PLD outputs are always valid
during warm reset, and they are valid in Power On
Reset once the internal PSD Configuration bits are
loaded. This loading of PSD is completed typically
long before the V
Once the PLD is active, the state of the outputs are
determined by the PSDabel equations.
Reset of Flash Memory Erase and Program
Cycles
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) termi-
nates the cycle and returns the Flash memory to
the READ Mode within a period of t
NLNH
. The same t
CC
OPR
Warm Reset
t NLNH-A
ramps up to operating level.
t NLNH
period is needed before the
NLNH-A
t OPR
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