PSD834F2-15M STMicroelectronics, PSD834F2-15M Datasheet - Page 73
PSD834F2-15M
Manufacturer Part Number
PSD834F2-15M
Description
Manufacturer
STMicroelectronics
Datasheet
1.PSD834F2-15M.pdf
(95 pages)
Specifications of PSD834F2-15M
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
52
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Figure 36. Synchronous Clock Mode Timing – PLD
Table 44. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
f
t
t
t
t
t
t
t
Symbol
MAX
S
H
CH
CL
CO
ARD
MIN
2. CLKIN (PD1) t
Maximum
Frequency
External Feedback
Maximum
Frequency
Internal Feedback
(f
Maximum
Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output
Delay
CPLD Array Delay
Minimum Clock
Period
CNT
Parameter
)
2
CLCL
REGISTERED
= t
OUTPUT
CLKIN
INPUT
CH
+ t
CL
Any macrocell
.
1/(t
Conditions
Clock Input
Clock Input
Clock Input
1/(t
1/(t
t
S
CH
+t
CH
S
+t
+t
CO
+t
CL
CO
–10)
CL
)
)
t CH
Min Max Min Max Min Max
20
15
10
25
0
-10
22.2
28.5
40.0
25
25
t CL
25
15
15
29
0
-15
t S
18.8
23.2
33.3
28
29
t H
30
16
16
32
t CO
0
-20
15.8
18.8
31.2
33
33
Aloc
+ 4
+ 4
PT
AI02860
Turbo
+ 20
Off
PSD834F2V
Slew
rate
– 6
1
MHz
MHz
MHz
Unit
73/95
ns
ns
ns
ns
ns
ns
ns