ISP1581BD NXP Semiconductors, ISP1581BD Datasheet - Page 23

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ISP1581BD

Manufacturer Part Number
ISP1581BD
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1581BD

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant

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Philips Semiconductors
Table 14:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
Endpoint Index register: bit allocation
R/W
7
-
9.2.5 DMA Configuration register (address: 38H)
9.2.6 DMA Hardware register (address: 3CH)
9.3.1 Endpoint Index register (address: 2CH)
reserved
9.3 Data flow registers
Table 13:
See
See
The Endpoint Index register selects a target endpoint for register access by the
microcontroller. The register consists of 1 byte and the bit allocation is shown in
Table
For example, to access the OUT data buffer of endpoint 1 via the Data Port register,
the Endpoint Index register has to be written first with 02H.
Bit
6
5
4
3
2
1
0
R/W
Endpoint MaxPacketSize
Endpoint Type
Buffer Length
Data Port
Short Packet
Control Function.
6
-
Section
Section
14. The following registers are indexed:
Interrupt Enable register: bit description
EP0SETUP
Symbol
IEDMA
IEHS_STA
IERESM
IESUSP
IEPSOF
IESOF
IEBRST
9.4.3.
9.4.4.
R/W
5
0
Rev. 06 — 23 December 2004
Description
A logic 1 enables interrupt upon DMA status change detection.
A logic 1 enables interrupt upon detection of a High Speed
Status change.
A logic 1 enables interrupt upon detection of a ‘resume’ state.
A logic 1 enables interrupt upon detection of a ‘suspend’ state.
A logic 1 enables interrupt upon detection of a Pseudo SOF.
A logic 1 enables interrupt upon detection of an SOF.
A logic 1 enables interrupt upon detection of a bus reset.
4
unchanged
3
ENDPIDX[3:0]
R/W
00H
Hi-Speed USB peripheral controller
…continued
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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