ISP1581BD NXP Semiconductors, ISP1581BD Datasheet - Page 43

• Manufacturer Part Number: ISP1581BD
• Manufacturer: NXP Semiconductors

Specifications of ISP1581BD

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
Table 55:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Power Reset
Bus Reset
Access
DMA Endpoint register: bit allocation
IE_1F0_
WF_E
R/W
7
0
0
R/W
9.4.9 DMA Endpoint register (address: 58H)
9.5.1 Interrupt register (address: 18H)
7
-
-
9.5 General registers
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in
Table 56:
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (02CH) at any time. Doing so would result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint.
However, if the DMA Endpoint register is pointed to an active endpoint, the firmware
must not reference the same endpoint on the Endpoint Index register.
The Interrupt register consists of 4 bytes. The bit allocation is given in
When a bit is set in the Interrupt register, this indicates that the hardware condition for
an interrupt has occurred. When the Interrupt register content is non-zero, the INT
output will be asserted. Upon detecting the interrupt, the external microprocessor
must read the Interrupt register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition,
various bus states can generate an interrupt: Resume, Suspend, Pseudo-SOF, SOF
and Bus Reset. The DMA Controller only has one interrupt bit: the source for a DMA
interrupt is shown in the DMA Interrupt Reason register (see
Each interrupt bit can be individually cleared by writing a logic 1. The DMA interrupt
bit can be cleared by writing a logic 1 to the related interrupt source bit in the DMA
Interrupt Reason register and writing a logic 1 to the DMA bit of the interrupt register.
IE_1F0_
Bit
7 to 4
3 to 1
0
WF_F
R/W
6
0
0
R/W
6
-
-
reserved
DMA Endpoint register: bit description
Symbol
-
EPIDX[2:0]
DMADIR
IE_1F0_
RF_E
R/W
5
0
0
R/W
Rev. 06 — 23 December 2004
5
-
-
READ_1F0
Description
reserved
selects the indicated endpoint for DMA access
0 — selects the RX/OUT FIFO for DMA read transfers
1 — selects the TX/IN FIFO for DMA write transfers.
R/W
IE_
R/W
4
0
0
4
-
-
IE_BSY_
DONE
Table
R/W
R/W
3
0
0
3
0
0
55.
Hi-Speed USB peripheral controller
RD_DONE
EPIDX[2:0]
IE_TF_
R/W
R/W
2
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2
0
0
Table
INTRQ_OK
IE_CMD_
R/W
R/W
1
0
0
1
0
0
51).
ISP1581
Table
reserved
DMADIR
57.
R/W
R/W
0
42 of 79
0
0
0
-
-