MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 108

• Manufacturer Part Number: MCIMX255AJM4A
• Manufacturer: Freescale

Specifications of MCIMX255AJM4A

• Lead Free Status / RoHS Status: Compliant

3.7.17.4
Figure 81
parameters (SS22–SS41) used in the figure.
Note:
108
• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
• All timings are on pads when SSI is being used for data transfer.
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
SS22
SS23
SS24
SS25
SS26
SS28
SS30
SS32
SS34
SS35
SS36
SS40
SS41
ID
shows the timing for SSI receiver with external clock.
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
FS (bl) low/high setup before (Tx) CK falling
FS (bl) low/high setup before (Tx) CK falling
FS (wl) low/high setup before (Tx) CK falling
FS (wl) low/high setup before (Tx) CK falling
(Tx/Rx) External FS rise time
(Tx/Rx) External FS fall time
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
AUDn_TXFS (wl)
AUDn_TXFS (bl)
SSI Receiver Timing with External Clock
AUDn_RXD
AUDn_TXC
(Input)
(Input)
(Input)
(Input)
Figure 81. SSI Receiver with External Clock Timing Diagram
i.MX25 Applications Processor for Automotive Products, Rev. 4
SS23
Table 82. SSI Receiver Timing with External Clock
Parameter
SS28
SS22
External Clock Operation
SS32
SS35
SS30
SS40
SS26
SS25
Table 82
SS41
–10.0
–10.0
Min.
81.4
36.0
36.0
10.0
10.0
10.0
2.0
—
—
—
—
describes the timing
SS24
SS36
SS34
Freescale Semiconductor
Max.
15.0
15.0
6.0
6.0
6.0
6.0
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns