MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 61

• Manufacturer Part Number: MCIMX255AJM4A
• Manufacturer: Freescale

Specifications of MCIMX255AJM4A

• Lead Free Status / RoHS Status: Compliant

3.7.6.1.3
The following diagrams and tables specify timing related to the SDRAMC module, which interfaces with
DDR2 SDRAM.
Freescale Semiconductor
SD21 DQS – DQ Skew (defines the data valid window in read cycles related to DQS)
SD22 DQS DQ HOLD time from DQS
SD23 DQS output access time from SDCLK posedge
ID
DQS (input)
DQ (input)
SDCLK
SDCLK
Figure 30. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
DDR2 SDRAM–Specific Parameters
Table 47. Mobile DDR SDRAM Read Cycle Timing Parameters
i.MX25 Applications Processor for Automotive Products, Rev. 4
SD23
SD21
Data
Parameter
SD22
Data
Data
Data
Data
Data
tDQSCK
Symbol
tDQSQ
tQH
Data
Min. Max. Unit
2.3
—
—
Data
0.85
6.7
—
ns
ns
ns
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