KSZ8851SNLI Micrel Inc, KSZ8851SNLI Datasheet - Page 13

• Manufacturer Part Number: KSZ8851SNLI
• Manufacturer: Micrel Inc

Specifications of KSZ8851SNLI

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Functional Description
The KSZ8851SNL is a single-chip Fast Ethernet MAC/PHY controller consisting of a 10/100 physical layer transceiver
(PHY), a MAC, and an industry standard Serial Peripheral Interface (SPI). The host CPU is via SPI interface to read/write
KSZ8851SNL internal registers either byte (8-bit), word (16-bit) or double word (32-bit) and to access KSZ8851SNL
RXQ/TXQ FIFOs for packet receive/transmit.
The KSZ8851SNL is fully compliant to IEEE802.3u standards.
Functional Overview
Power Management
The KSZ8851SNL supports enhanced power management feature in low power state with energy detection to ensure low-
power dissipation during device idle periods. There are four operation modes under the power management function
which is controlled by two bits in PMECR (0xD4) register as shown below:
PMECR[1:0] = 00 Normal Operation Mode
PMECR[1:0] = 01 Energy Detect Mode
PMECR[1:0] = 10 Soft Power Down Mode
PMECR[1:0] = 11 Power Saving Mode
Table 1 indicates all internal function blocks status under four different power management operation modes.
Normal Operation Mode
This is the default setting bit[1:0]=00 in PMECR register after the chip power-up or hardware reset (pin 67). When
KSZ8851SNL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is
ready for CPU read or write.
During the normal operation mode, the host CPU can set the bit[1:0] in PMECR register to transit the current normal
operation mode to any one of the other three power management operation modes.
Energy Detect Mode
The energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8851SNL is not connected to an active link partner. For example, if cable is not present or it is connected to a
powered down partner, the KSZ8851SNL can automatically enter to the low power state in energy detect mode. Once
activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851SNL can automatically
power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8851SNL reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The
energy detect mode is entered by setting bit[1:0]=01 in PMECR register. When the KSZ8851SNL is in this mode, it will
monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit[7:0] Go-
Sleep time in GSWUTR register, KSZ8851SNL will go into a low power state. When KSZ8851SNL is in low power state, it
will keep monitoring the cable energy. Once the energy is detected from the cable and is continuously presented for a
time longer than pre-configured value at bit[15:8] Wake-Up time in GSWUTR register, the KSZ8851SNL will enter either
the normal power state if the auto-wakeup enable bit[7] is set in PMECR register or the normal operation mode if both
auto-wakeup enable bit[7] and wakeup to normal operation mode bit[6] are set in PMECR register.
August 2009
Micrel, Inc.
Internal PLL Clock
Tx/Rx PHY
MAC
SPI Interface
Function Blocks
KSZ8851SNL
Normal mode
Enabled
Enabled
Enabled
Enabled
Table 1. Internal Function Blocks Status
Rx unused block disabled
Power saving mode
Enabled
Enabled
Enabled
Power Management Operation Modes
13
Energy detect mode
Energy detect at Rx
Disabled
Disabled
Disabled
Soft power down mode
KSZ8851SNL/SNLI
Disabled
Disabled
Disabled
Disabled
M9999-083109-2.0