KSZ8851SNLI Micrel Inc, KSZ8851SNLI Datasheet - Page 6

• Manufacturer Part Number: KSZ8851SNLI
• Manufacturer: Micrel Inc

Specifications of KSZ8851SNLI

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Micrel, Inc.
KSZ8851SNL/SNLI
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 ................................................................................ 46
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 ................................................................................ 46
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3................................................................................ 47
0x5C – 0x5F: Reserved .................................................................................................................................................. 47
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 ........................................................................................ 47
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 ........................................................................................ 47
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 ................................................................................ 47
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 ................................................................................ 47
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 ................................................................................ 47
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3................................................................................ 48
0x6C – 0x6F: Reserved .................................................................................................................................................. 48
Transmit Control Register (0x70 – 0x71): TXCR............................................................................................................ 48
Transmit Status Register (0x72 – 0x73): TXSR ............................................................................................................. 48
Receive Control Register 1 (0x74 – 0x75): RXCR1 ....................................................................................................... 49
Receive Control Register 2 (0x76 – 0x77): RXCR2 ....................................................................................................... 50
TXQ Memory Information Register (0x78 – 0x79): TXMIR ............................................................................................ 51
0x7A – 0x7B: Reserved .................................................................................................................................................. 51
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR ............................................................................... 51
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR...................................................................... 52
TXQ Command Register (0x80 – 0x81): TXQCR .......................................................................................................... 52
RXQ Command Register (0x82 – 0x83): RXQCR.......................................................................................................... 53
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR............................................................................................. 54
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR............................................................................................ 54
0x88 – 0x8B: Reserved .................................................................................................................................................. 55
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR ................................................................................. 55
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR ............................................................................ 55
Interrupt Enable Register (0x90 – 0x91): IER ................................................................................................................ 55
Interrupt Status Register (0x92 – 0x93): ISR ................................................................................................................. 56
0x94 – 0x9B: Reserved .................................................................................................................................................. 57
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR................................................................................. 57
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR ................................................................................... 57
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0.................................................................................... 58
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1.................................................................................... 58
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2.................................................................................... 58
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3.................................................................................... 58
0xA8 – 0xAF: Reserved.................................................................................................................................................. 58
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR.................................................................................... 58
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR................................................................................... 59
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR............................................................................. 59
0xB6 – 0xBF: Reserved.................................................................................................................................................. 59
Chip ID and Enable Register (0xC0 – 0xC1): CIDER .................................................................................................... 59
0xC2 – 0xC5: Reserved ................................................................................................................................................. 59
Chip Global Control Register (0xC6 – 0xC7): CGCR..................................................................................................... 59
Indirect Access Control Register (0xC8 – 0xC9): IACR ................................................................................................. 59
0xCA – 0xCF: Reserved ................................................................................................................................................. 60
August 2009
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M9999-083109-2.0