ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet - Page 168

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ML610Q422-NNNTBZ03A7

Manufacturer Part Number
ML610Q422-NNNTBZ03A7
Description
MCU 8BIT 32K FLASH 22CH 120-TQFP
Manufacturer
Rohm Semiconductor
Series
-r

Specifications of ML610Q422-NNNTBZ03A7

Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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12.2.2
Address: 0F00EH
Access: W
Access size: 8 bits
Initial value: 00H
WDTCON is a special function register (SFR) to clear the WDT counter.
When WDTCON is read, the value of the internal pointer (WDP) is read from bit 0.
[Description of Bits]
• WDP/d0 (bit 0)
• d7-d0 (bits 7-0)
Note:
When the WDT interrupt (WDTINT) occurs by the first WDT counter overflow, the counter and the internal pointer
(WDP) are initialiaed for a half cycle of low speed clock (about 15us). During the time period that they are initialized,
writing to WDTCON is disable and the logic of WDP does not change. Therefore, in the case of that you have
program codes handle to clear the WDT when the first overflow WDT interrupt occurs and also the codes run at
high-speed system clock, please check the WDP gets reversed after writing to WDTCON to see if the writing was
surely successful. For example of the program code, see Section 12.3.1, "Handling example when you do not want to
use the watch dog timer".
Initial value
WDTCON
The value of the internal pointer (WDP) is read from this bit. The WDP is reset to “0” at the system reset or Watch
Dog Timer overflow and is inverted every writing to WDTCON.
This bit is used to write data to clear the WDT counter. Write “5AH” on the condition of WDP is “0” and write
“0A5H” on the condition of WDP is “1”.
R/W
Watchdog Timer Control Register (WDTCON)
R/W
d7
7
0
R/W
d6
6
0
R/W
d5
5
0
R/W
d4
12 – 3
4
0
R/W
d3
0
3
ML610Q431/ML610Q432 User’s Manual
R/W
d2
2
0
Chapter 13 Watchdog Timer
R/W
d1
1
0
WDP/d0
R/W
0
0

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