ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet - Page 218

• Manufacturer Part Number: ML610Q422-NNNTBZ03A7
• Description: MCU 8BIT 32K FLASH 22CH 120-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q422-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.3 Description of Operation
15.3.1
15.3.1.1
15.3.1.2
15.3.1.3
15.3.1.4
15.3.1.5
15.3.1.6
Communication is started when communication mode is selected by using the I
I
bus 0 slave address register, and “1” is written to the I20ST bit of the I2C bus 0 control register (I2C0CON).
When “1” is written to the I20ST bit of the I
I20ST bit is “0”), communication is started and the start condition waveform is output to the SDA and SCL pins.
After execution of the start condition, the LSI shifts to slave address transmit mode.
When “1” is written to the I20RS and I20ST bits of the I
(the I20ST bit is “0”), the repeated start condition waveform is output to the SDA and SCL pins. If you want to
continue the communication without making the stop condition, executing the repeated start condition enables to
specify another slave addresses or change the data direction (transmit or receive) See Figure 15-4.
After execution of the repeated start condition, the LSI shifts to slave address transmit mode.
In slave address transmit mode, the values (slave address and data communication direction) of the I
address register (I2C0SA) are transmitted in MSB first, and finally, the acknowledgment signal is received in the
I20ACR bit of the I
acknowledgment “0” and set to “1” when receving an acknowledgment “1”.
At completion of acknowledgment reception, the LSI shifts to the I
state (control register setting wait state).
The value of I2C0SA output from the SDA pin is stored in I2C0RD during aftermentioned Control Register Setting
Wait State.
In data transmit mode, the value of I2C0TD is transmitted in MSB first, and finally, the acknowledgment signal is
received in the I20ACR bit of the I
acknowledgment “0” and set to “1” when receving an acknowledgment “1”.
At completion of acknowledgment reception, the LSI shifts to the I
state (control register setting wait state).
The value of I2C0TD output from the SDA pin is stored in I2C0RD.
In data receive mode, the value input in the SDA pin is received synchronously with the rising edge of the serial clock
output to the SCL pin, and finally, the value of the I20ACT bit of the I2C bus 0 control register (I2C0CON) is output as
an acknowledge signal. For example, as shown in Figure 15-3 and Figure 15-4, the acknowlege slot after I20ACT bit is
reset to “0” (I2CON=”01H”) will have the acknowlege “0” (Shown as “A” in the Figure). In the same way, the
acknowlege slot after I20ACT bit is set to “1” (I2CON=”81H”) will have the non-acknowlege “1” (Shown as “A” in the
Figure).
At completion of acknowledgment transmission, the LSI shifts to the I
state (control register setting wait state).
The data received is stored in I2C0RD after the acknowledgment signal is output. The acknowledgment signal output
is received in the I20ACR bit of the I
When the LSI shifts to the control register setting wait state, an I
In the control register setting wait state, the transmit flag (I20ER) of the I
acknowledgment receive data (I20ACR) are confirmed and at data reception, the contents of I2C0RD are read in the
CPU and the next operation mode is selected.
2
C function is enabled by using the I20EN bit, a slave address and a data communication direction are set in the I
Communication Operating Mode
Start Condition
Repeated Start Condition
Slave Address Transmit Mode
Data Transmit Mode
Data Receive Mode
Control Register Setting Wait State
2
C bus 0 status register (I2CSTAT). The I20ACR bit is reset to “0” when receving an
2
C bus 0 status register (I2CSTAT). The I20ACR bit is reset to “0” when receving an
2
C bus 0 status register (I2CSTAT).
2
C bus 0 control register ((I2C0CON) while communication is stopped (the
15 – 10
2
C bus 0 control register ((I2C0CON) during communication
2
C bus interface interrupt (I2C0INT) is generated.
2
2
C bus 0 control register (I2C0CON) setting wait
C bus 0 control register (I2C0CON) setting wait
2
C bus 0 control register (I2C0CON) setting wait
ML610Q421/ML610Q422 User’s Manual
2
C bus 0 status register (I2C0STAT) and
2
C bus 0 mode register (I2C0MOD), the
Chapter 15 I
2
C Bus Interface
2
C bus 0 slave
2
C