ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet - Page 171

• Manufacturer Part Number: ML610Q422-NNNTBZ03A7
• Description: MCU 8BIT 32K FLASH 22CH 120-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q422-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 12-2 shows an example of watchdog timer operation.
1 The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start.
2 The overflow period of the WDT counter (TWOV) is set to WDTMOD.
3 “5AH” is written to WDTCON. (Internal pointer 0→1)
4 “0A5H” is written to WDTCON and the WDT counter is cleared. (Internal pointer 1→0)
5 “5AH” is written o WDTCON. (Internal pointer 0→1)
6 When “5AH” is written to WDTCON after the occurrence of abnormality, it cannot be accepted as the internal
7 Although “0A5H” is written to WDTCON, the WDT counter is not cleared since the internal pointer is “0” and the
8 The WDT counter overflows and a watchdog timer interrupt request (WDTINT) is generated. In this case,, the
9 If the WDT counter is not cleared even by the software processing performed following a watchdog timer interrupt
Note:
• In STOP mode, the watchdog timer operation also stops.
• In HALT mode, the watchdog timer operation does not stop. When the WDT interrupt occurs, the HALT mode is
• The watchdog timer cannot detect all the abnormal operations. Even if the CPU loses control, the watchdog timer
released.
cannot detect the abnormality in the operation state in which the WDT counter is cleared.
pointer is set to “1”. (Internal pointer 1→0)
writing of “5AH” is not accepted in 6. (Internal pointer 0→1)
WDT counter and the internal pointer (WDP) are initialiaed for a half cycle of low speed clock (about 15.26us).
and the WDT counter overflows again, WDT reset occurs and the mode is shifted to a system reset mode.
WDTCON Write
Internal pointer
WDT interrupt
WDT counter
System reset
WDT reset
RESET_S
WDTINT
WDTP
oscillation start
Low-speed
Data:
Figure 12-2 Example of Watchdog Timer Operation
2WDTMOD
5A
3
setting
A5
4
Occurrence of
Overflow period
abnormality
5A
5
T
WOV
5A
6
12 – 6
A5
7
8Occurrence of
Overflow period
WDTINT
ML610Q431/ML610Q432 User’s Manual
Overflow
T
WOV
Chapter 13 Watchdog Timer
Program
9Occurrence of
start
WDT reset
WDTMOD
5A
setting
A5