AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 12

IC CLOCK DIST 8OUT PLL 64LFCSP

AD9510BCPZ

Manufacturer Part Number
AD9510BCPZ
Description
IC CLOCK DIST 8OUT PLL 64LFCSP
Manufacturer
Analog Devices Inc
Type
Fanout Buffer (Distribution), Divider, PLLr
Datasheet

Specifications of AD9510BCPZ

Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
Yes/Yes
Input
Clock
Output
CMOS, LVDS, LVPECL
Frequency - Max
1.2GHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.2GHz
Clock Ic Type
Clock Distribution
Ic Interface Type
Serial
Frequency
1.2GHz
No. Of Outputs
8
No. Of Multipliers / Dividers
8
Supply Voltage Range
3.135V To 3.465V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9510BCPZ
Manufacturer:
AD
Quantity:
855
Part Number:
AD9510BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9510
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 6.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
LVDS OUTPUT ADDITIVE TIME JITTER
CLK1 = 622.08 MHz
CLK1 = 622.08 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT3) = 622.08 MHz
Divide Ratio = 1
Any LVPECL (OUT0 to OUT3) = 155.52 MHz
Divide Ratio = 4
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 100 MHz
All LVDS (OUT4 to OUT7) = 100 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
All LVDS (OUT4 to OUT7) = 50 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs Off)
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs On)
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4
Rev. A | Page 12 of 60
Min
Typ
40
55
215
215
222
225
225
264
319
Max
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Distribution Section only;
does not include PLL or external VCO/VCXO
BW = 12 kHz − 20 MHz (OC-12)
BW = 12 kHz − 20 MHz (OC-3)
Calculated from SNR of ADC method;
F
Calculated from SNR of ADC method;
F
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
F
Interferer(s)
Calculated from SNR of ADC method;
F
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
F
Interferer(s)
Distribution Section only;
does not include PLL or external VCO/VCXO
Calculated from SNR of ADC method;
F
Calculated from SNR of ADC method;
F
Test Conditions/Comments
Interferer(s)
Interferer(s)
C
C
C
C
C
C
C
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
IN
IN
IN
IN
IN
IN
IN
= 170 MHz
= 170 MHz
= 170 MHz
= 170 MHz
= 170 MHz
= 170 MHz
= 170 MHz

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