AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 51

• Manufacturer Part Number: AD9510BCPZ
• Description: IC CLOCK DIST 8OUT PLL 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9510BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 8
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Reg.
Addr.
(Hex) Bit(s) Name
0A
0A
0A
0A
0B
0C
0D
0D
0D
0D
0D
0E-33
34
(38)
34
(38)
35
<4:2> Prescaler Value
<5>
<6>
<7>
<5:0> 14-Bit Reference
<7:0> 14-Bit Reference
<1:0> Antibacklash Pulse
<4:2>
<5>
<6>
<7>
<0>
<7:1>
<2:0> Ramp Current
(P/P+1)
B Counter Bypass
Counter, MSBs
Counter, R LSBs
Width
Digital Lock Detect
Window
Digital Lock Detect
Window
Lock Detect
Disable
Unused
Fine Delay Adjust
Delay Control
OUT5
(OUT6)
OUT5
Description
<4>
0
0
0
0
1
1
1
1
DM = Dual Modulus, FD = Fixed Divide.
Not Used
Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the B counter is
divided by 1. This allows the prescaler setting to determine the divide for the N divider.
Not Used
R Divider (MSB) <13:8>
R Divider (MSB) <7:0>
<1>
0
0
1
1
Not Used
<5>
0 (Default)
1
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window
time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the
loss-of-lock threshold.
0 = Normal Lock Detect Operation (Default)
1 = Disable Lock Detect
Not Used
Not Used
Delay Block Control Bit
Bypasses Delay Block and Powers It Down (Default = 1b)
Not Used
The slowest ramp (200 μA) sets the longest full scale of approximately 10 ns.
<3>
0
0
1
1
0
0
1
1
<0>
0
1
0
1
Digital Lock Detect Window (ns)
9.5
3.5
<2>
0
1
0
1
0
1
0
1
Mode
FD
FD
DM
DM
DM
DM
DM
FD
Rev. A | Page 51 of 60
Antibacklash Pulse Width (ns)
1.3 (Default)
2.9
6.0
1.3
Prescaler Mode
Divide by 1
Divide by 2
2/3
4/5
8/9
16/17
32/33
Divide by 3
Digital Lock Detect Loss-of-Lock Threshold (ns)
15
7
AD9510