AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 47

• Manufacturer Part Number: AD9510BCPZ
• Description: IC CLOCK DIST 8OUT PLL 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9510BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 8
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Addr
(Hex)
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46, 47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
Parameter
Delay Fine
Adjust 6
OUTPUTS
LVPECL OUT0
LVPECL OUT1
LVPECL OUT2
LVPECL OUT3
LVDS_CMOS
OUT 4
LVDS_CMOS
OUT 5
LVDS_CMOS
OUT 6
LVDS_CMOS
OUT 7
CLK1 AND
CLK2
Clocks Select,
Power-Down
(PD) Options
DIVIDERS
Divider 0
Divider 0
Divider 1
Divider 1
Divider 2
Divider 2
Divider 3
Divider 3
Divider 4
Divider 4
Divider 5
Divider 5
Divider 6
Bit 7 (MSB)
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Low Cycles <7:4>
Low Cycles <7:4>
Low Cycles <7:4>
Low Cycles <7:4>
Low Cycles <7:4>
Low Cycles <7:4>
Low Cycles <7:4>
Bit 6
Sync
Sync
Sync
Sync
Sync
Sync
No
No
No
No
No
No
Not Used
Not Used
Not Used
Not Used
Bit 5
CLKs in
Force
Force
Force
Force
Force
Force
PD
Rev. A | Page 47 of 60
Bit 4
Driver On
Driver On
Driver On
Driver On
REFIN PD
Start H/L
Start H/L
Start H/L
Start H/L
Start H/L
Start H/L
Inverted
Inverted
Inverted
Inverted
CMOS
CMOS
CMOS
CMOS
Not Used
Not Used
Not Used
5-Bit Fine Delay <5:1>
Bit 3
Select
Select
Select
Select
Logic
Logic
Logic
Logic
CLK
PLL
PD
Output Level
Output Level
Output Level
Output Level
to
<3:2>
<3:2>
<3:2>
<3:2>
Bit 2
CLK2
Phase Offset <3:0>
Phase Offset <3:0>
Phase Offset <3:0>
Phase Offset <3:0>
Phase Offset <3:0>
Phase Offset <3:0>
High Cycles <3:0>
High Cycles <3:0>
High Cycles <3:0>
High Cycles <3:0>
High Cycles <3:0>
High Cycles <3:0>
High Cycles <3:0>
PD
Output Level
Output Level
Output Level
Output Level
<2:1>
<2:1>
<2:1>
<2:1>
Bit 1
Power-Down <1:0>
Power-Down <1:0>
Power-Down <1:0>
Power-Down <1:0>
CLK1
PD
Bit 0
(LSB)
Output
Output
Output
Output
Power
Power
Power
Power
CLK IN
Select
Used
Not
Def.
Value
(Hex)
00
04
0A
08
08
08
02
02
03
03
01
00
00
00
00
11
00
33
00
00
00
11
00
00
AD9510
Notes
Min. Delay
Value
OFF
ON
ON
ON
LVDS, ON
LVDS, ON
LVDS, OFF
LVDS, OFF
Input
Receivers
All Clocks
ON, Select
CLK1
Divide by 2
Phase = 0
Divide by 2
Phase = 0
Divide by 4
Phase = 0
Divide by 8
Phase = 0
Divide by 2
Phase = 0
Divide by 4
Phase = 0
Divide by 2