AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 44

• Manufacturer Part Number: AD9510BCPZ
• Description: IC CLOCK DIST 8OUT PLL 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9510BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 8
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9510
Table 21. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/ W
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
CSB
CSB
SDO
CSB
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
SCLK
SDIO
CSB
I14
W1
DON'T CARE
R/W
DON'T CARE
DON'T CARE
W1
R/W
A0 A1 A2 A3
W0
I13
W0
16-BIT INSTRUCTION HEADER
W1
A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
W0
I12
A12 = 0
A12
t
S
R/W
A11 A10 A9 A8 A7
A4
16-BIT INSTRUCTION HEADER
16-BIT INSTRUCTION HEADER
t
A5 A6 A7 A8 A9 A10 A11 A12
DS
Figure 48. Serial Control Port Write−MSB First, 16-Bit Instruction, Timing Measurements
W1
I11
A11 = 0
Figure 46. Serial Control Port Write—MSB First, 16-Bit Instruction, 2 Bytes Data
Figure 47. Serial Control Port Read—MSB First, 16-Bit Instruction, 4 Bytes Data
Figure 50. Serial Control Port Write—LSB First, 16-Bit Instruction, 2 Bytes Data
SCLK
SDIO
SDO
W0
CSB
t
DH
Figure 49. Timing Diagram for Serial Control Port Register Read
A12
A6 A5
I10
A10 = 0
A11
t
HI
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
A4 A3 A2
REGISTER (N) DATA
DATA BIT N
A10
t
LO
W0
t
Rev. A | Page 44 of 60
I9
A9 = 0
DV
A9
W1
A1 A0
t
CLK
R/W
A8
D0
D7 D6 D5 D4 D3
DATA BIT N– 1
REGISTER (N – 1) DATA
I8
A8 = 0
A7
D1
REGISTER (N) DATA
REGISTER (N) DATA
D2 D3 D4
A6
I7
A7 = 0
A5
D2 D1 D0 D7
D5 D6 D7 D0
D4
REGISTER (N – 2) DATA
I6
A6
D3
D2
I5
A5
D6 D5
REGISTER (N – 1) DATA
D1 D2
REGISTER (N + 1) DATA
D1
I4
A4
D4 D3 D2
D3 D4 D5
D0
REGISTER (N – 3) DATA
t
I3
A3
H
D1 D0
D6
DON'T CARE
DON'T CARE
I2
A2
D7
DON'T CARE
DON'T CARE
I1
A1
DON'T CARE
DON'T CARE
DON'T CARE
DON'T
CARE
LSB
I0
A0