AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 4

• Manufacturer Part Number: AD9510BCPZ
• Description: IC CLOCK DIST 8OUT PLL 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9510BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 8
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9510
SPECIFICATIONS
Typical (typ) is given for V
Minimum (min) and maximum (max) values are given over full V
PLL CHARACTERISTICS
Table 1.
Parameter
REFERENCE INPUTS (REFIN)
PHASE/FREQUENCY DETECTOR (PFD)
CHARGE PUMP (CP)
RF CHARACTERISTICS (CLK2)
CLK2 VS. REFIN DELAY
PRESCALER (PART OF N DIVIDER)
PFD Input Frequency
PFD Input Frequency
PFD Input Frequency
Antibacklash Pulse Width
Antibacklash Pulse Width
Antibacklash Pulse Width
Input Frequency
Input Sensitivity
Input Common-Mode Range, V
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Prescaler Input Frequency
CLK2 Input Frequency for PLL
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFINB
Input Resistance, REFIN
Input Resistance, REFINB
Input Capacitance
I
I
Sink-and-Source Current Matching
I
I
Input Common-Mode Voltage, V
CP
CP
CP
CP
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
High Value
Low Value
Absolute Accuracy
CPR
Sink/Source
Three-State Leakage
vs. V
vs. Temperature
SET
CP
Range
S
= 3.3 V ± 5%; V
2
CMR
CM
Min
0
1.45
1.40
4.0
4.5
1.5
1.3
4.0
S
≤ VCP
1.60
1.50
4.9
5.4
2
2.7/10
2
1.5
1.6
150
4.8
500
Typ
150
1.3
2.9
6.0
4.8
0.60
2.5
1
2
150
2
S
≤ 5.5 V, T
Rev. A | Page 4 of 60
A
= 25°C, R
S
and T
Max
250
1.75
1.60
5.8
6.3
100
100
45
1.6
1.7
1.8
5.6
600
1000
1600
1600
1600
300
A
SET
(−40°C to +85°C) variation.
Unit
MHz
mV p-p
V
V
kΩ
kΩ
pF
MHz
MHz
MHz
ns
ns
ns
mA
mA
%
kΩ
nA
%
%
%
GHz
mV p-p
V
V
mV p-p
kΩ
pF
ps
MHz
MHz
MHz
MHz
MHz
MHz
= 4.12 kΩ, CPR
Self-bias voltage of REFIN
Self-bias voltage of REFINB
Test Conditions/Comments
Self-biased
Self-biased
Antibacklash pulse width 0Dh<1:0> = 00b.
Antibacklash pulse width 0Dh<1:0> = 01b.
Antibacklash pulse width 0Dh<1:0> = 10b.
0Dh<1:0> = 00b (this is the default setting).
0Dh<1:0> = 01b.
0Dh<1:0> = 10b.
Programmable.
With CPR
V
0.5 < V
0.5 < V
V
Frequencies > 1200 MHz (LVPECL) or 800 MHz
(LVDS) require a minimum divide-by-2 (see the
Distribution Section).
Self-biased; enables ac coupling.
With 200 mV p-p signal applied.
CLK2 ac-coupled; CLK2B capacitively
bypassed to RF ground.
Self-biased.
Difference at PFD.
See the VCO/VCXO Feedback Divider—N (P, A, B)
section.
A, B counter input frequency.
CP
CP
= VCPs/2.
= VCPs/2 V.
SET
CP
CP
< VCPs − 0.5 V.
< VCPs − 0.5 V.
SET
= 5.1 kΩ, unless otherwise noted.
1
1
.
.
= 5.1 kΩ.
1
.
1
.